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authorBob Wilson <bob.wilson@apple.com>2010-03-23 05:25:43 +0000
committerBob Wilson <bob.wilson@apple.com>2010-03-23 05:25:43 +0000
commit340861d29e954e9428c32856d03b3fb01aa5d864 (patch)
tree08f4e83d19a246b75229f5fd2493880de2f37531 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
parent995891667f37fccdd21a8a5a737425e83afcd616 (diff)
downloadbcm5719-llvm-340861d29e954e9428c32856d03b3fb01aa5d864.tar.gz
bcm5719-llvm-340861d29e954e9428c32856d03b3fb01aa5d864.zip
Change VLD1 instructions for loading Q register values to operate on pairs
of D registers. Add a separate VLD1q instruction with a Q register destination operand for use by loadRegFromStackSlot. llvm-svn: 99261
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e6ea03aa4aa..943952fcf6b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -788,7 +788,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
if (Align >= 16
&& (getRegisterInfo().canRealignStack(MF))) {
- AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
+ AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
.addFrameIndex(FI).addImm(128)
.addMemOperand(MMO));
} else {
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