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* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+1
| | | | | | | | Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-1/+2
| | | | llvm-svn: 158164
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
| | | | | | Match expectations of the new latency API. Cleanup and make the logic consistent. llvm-svn: 158163
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
| | | | llvm-svn: 158162
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
| | | | llvm-svn: 158161
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-8/+11
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Mark a static table as const. Shrink opcode size in static tables to ↵Craig Topper2012-05-241-14/+9
| | | | | | uint16_t. Simplify loop iterating over one of those tables. No functional change intended. llvm-svn: 157367
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-27/+119
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-118/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-27/+118
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.Jakob Stoklund Olesen2012-04-041-0/+23
| | | | | | | | | | A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
| | | | | | | | | | | | | ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> llvm-svn: 153686
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-281-2/+2
| | | | | | | | | The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. llvm-svn: 153603
* ARM has a peephole optimization which looks for a def / use pair. The defEvan Cheng2012-03-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | produces a 32-bit immediate which is consumed by the use. It tries to fold the immediate by breaking it into two parts and fold them into the immmediate fields of two uses. e.g movw r2, #40885 movt r3, #46540 add r0, r0, r3 => add.w r0, r0, #3019898880 add.w r0, r0, #30146560 ; However, this transformation is incorrect if the user produces a flag. e.g. movw r2, #40885 movt r3, #46540 adds r0, r0, r3 => add.w r0, r0, #3019898880 adds.w r0, r0, #30146560 Note the adds.w may not set the carry flag even if the original sequence would. rdar://11116189 llvm-svn: 153484
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+1
| | | | llvm-svn: 153422
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-18/+18
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
| | | | | | | | | | When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. llvm-svn: 152095
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-25/+25
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
| | | | | | | | | | | MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. llvm-svn: 152008
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+4
| | | | | | | | | | | | | | Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 llvm-svn: 151673
* Clarify ARM calling conventions.Jakob Stoklund Olesen2012-02-221-0/+2
| | | | llvm-svn: 151113
* Calls don't really change the stack pointer.Jakob Stoklund Olesen2012-02-211-1/+2
| | | | | | | Even if a call instruction has %SP<imp-def> operands, it doesn't change the value of the stack pointer. llvm-svn: 151104
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen2012-02-171-6/+8
| | | | llvm-svn: 150833
* Fix ARMBaseInstrInfo::getInstrLatency for calls.Jakob Stoklund Olesen2012-02-171-1/+1
| | | | | | Calls always clobber CPSR. llvm-svn: 150831
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-3/+1
| | | | llvm-svn: 149961
* DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng2012-02-051-1/+1
| | | | llvm-svn: 149846
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-85/+81
| | | | llvm-svn: 148578
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-2/+3
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-031-3/+2
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-211-6/+12
| | | | llvm-svn: 147069
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-201-2/+3
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. llvm-svn: 146997
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-141-14/+41
| | | | | | | | | | | r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-8/+129
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-12/+24
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-12/+11
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Revert r145971: "Use conservative size estimate for tBR_JTr."Jakob Stoklund Olesen2011-12-061-3/+3
| | | | | | This caused more offset errors. llvm-svn: 145980
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-2/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Use conservative size estimate for tBR_JTr.Jakob Stoklund Olesen2011-12-061-3/+3
| | | | | | | | | | This pseudo-instruction contains a .align directive in its expansion, so the total size may vary by 2 bytes. It is too difficult to accurately keep track of this alignment directive, just use the worst-case size instead. llvm-svn: 145971
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-6/+12
| | | | llvm-svn: 145510
* Enable -widen-vmovs by default.Jakob Stoklund Olesen2011-11-151-1/+1
| | | | | | | | | | | This will widen 32-bit register vmov instructions to 64-bit when possible. The 64-bit vmovd instructions can then be translated to NEON vorr instructions by the execution dependency fix pass. The copies are only widened if they are marked as clobbering the whole D-register. llvm-svn: 144734
* Make use of MachinePointerInfo::getFixedStack. This removes all mentionJay Foad2011-11-151-4/+2
| | | | | | of PseudoSourceValue from lib/Target/. llvm-svn: 144632
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-1/+2
| | | | | | Four entry register lists. llvm-svn: 142882
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-241-1/+0
| | | | llvm-svn: 142877
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-2/+2
| | | | | | Three entry register list variation. llvm-svn: 142876
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-8/+16
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-181-1/+0
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* Fix -widen-vmovs liveness issues.Jakob Stoklund Olesen2011-10-121-3/+29
| | | | | | | | | | | | | | | | | | | | | | When widening a copy, we are reading a larger register that may not be live. Use an <undef> flag to tell the register scavenger and machine code verifier that we know the value isn't defined. We now widen: %S6<def> = COPY %S4<kill>, %D3<imp-def> into: %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill> This also keeps the <kill> flag on %S4 so we don't inadvertently kill a live value in %S5. Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves the <undef> flag when converting VMOVD to VORR. llvm-svn: 141746
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