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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-4/+9
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-091-9/+4
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-091-4/+9
* [ARM] Add some VCMP folding and canonicalisationDavid Green2019-12-021-19/+0
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-2/+2
* Reland: [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-11-081-16/+10
* Revert rG57ee0435bd47f23f3939f402914c231b4f65ca5e - [TII] Use optional destin...Simon Pilgrim2019-10-311-10/+16
* [TII] Use optional destination and source pair as a return value; NFCDjordje Todorovic2019-10-311-16/+10
* [ARM][AArch64][DebugInfo] Improve call site instruction interpretationDjordje Todorovic2019-10-301-0/+26
* [IfCvt][ARM] Optimise diamond if-conversion for code sizeOliver Stannard2019-10-101-0/+32
* ARMBaseInstrInfo getOperandLatency - silence static analyzer dyn_cast<> null ...Simon Pilgrim2019-09-261-2/+2
* [ARM] Prevent generating NEON stack accesses under MVE.David Green2019-09-091-4/+8
* [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia...David Green2019-09-031-0/+47
* [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions.David Green2019-09-031-1/+5
* Bug fix on function epilog optimization (ARM backend)Oliver Stannard2019-09-031-2/+3
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-42/+42
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-13/+12
* [ARM] Lower "(x<<c) > 0x80000000U" to "lsls" on Thumb1.Eli Friedman2019-07-311-0/+1
* [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.Simon Tatham2019-06-271-4/+4
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-10/+106
* [ARM] Add MVE vector load/store instructions.Simon Tatham2019-06-251-1/+4
* [ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT.Huihui Zhang2019-06-181-5/+5
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-111-0/+6
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-4/+5
* [ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASMNick Desaulniers2019-05-241-10/+10
* [ARM] Update check for CBZ in IfcvtDavid Green2019-04-231-13/+45
* [ARM] Don't replicate instructions in Ifcvt at minsizeDavid Green2019-04-231-0/+9
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-3/+3
* [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz.Eli Friedman2019-04-011-0/+2
* [ARM] Don't confuse the scheduler for very large VLDMDIA etc.Eli Friedman2019-03-271-1/+6
* [ARM] Add missing memory operands to a bunch of instructions.Eli Friedman2019-03-251-2/+4
* [ARM] Don't form "ands" when it isn't scheduled correctly.Eli Friedman2019-03-221-1/+9
* [ARM] Add MachineVerifier logic for some Thumb1 instructions.Eli Friedman2019-03-151-0/+25
* [ARM] Add some more missing T1 opcodes for the peephole optimisierDavid Green2019-02-251-12/+24
* [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPsDavid Green2019-02-221-11/+54
* Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole optim...David Green2019-02-211-54/+12
* [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPsDavid Green2019-02-211-12/+54
* [ARM] Ensure we update the correct flags in the peephole optimiserDavid Green2019-02-141-2/+5
* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-1/+1
* [ARM] Reformat isRedundantFlagInstr for D57833. NFCDavid Green2019-02-071-8/+4
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] Add missing pseudo-instruction for Thumb1 RSBS.Eli Friedman2018-10-311-0/+1
* [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1.Eli Friedman2018-10-261-0/+2
* [ARM] Account for implicit IT when calculating inline asm sizePeter Smith2018-10-081-2/+6
* X86, AArch64, ARM: Do not attach debug location to spill/reload instructionsMatthias Braun2018-10-051-15/+15
* Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instr...Matt Morehouse2018-10-021-15/+15
* X86, AArch64, ARM: Do not attach debug location to spill/reload instructionsMatthias Braun2018-10-011-15/+15
* llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song2018-09-271-3/+2
* Remove FrameAccess struct from hasLoadFromStackSlotSander de Smalen2018-09-051-4/+8
* Extend hasStoreToStackSlot with list of FI accesses.Sander de Smalen2018-09-031-4/+12
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