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authorSimon Tatham <simon.tatham@arm.com>2019-06-27 12:41:12 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-06-27 12:41:12 +0000
commit1a3dc8f678499dd14daf5170df3adf2e646c0933 (patch)
tree6fbf9711a3401fc30af969d2c4057f8c23728b54 /llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
parentffb2b347ffbdc667169af4f4627cfdf7d64be6a0 (diff)
downloadbcm5719-llvm-1a3dc8f678499dd14daf5170df3adf2e646c0933.tar.gz
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[ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.
The code to generate register move instructions in and out of VPR and FPSCR_NZCV had assertions checking that the other register involved was a GPR _pair_, instead of a single GPR as it should have been. Reviewers: miyuki, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63865 llvm-svn: 364534
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index de8a04632f5..222aa85856a 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -927,25 +927,25 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
return;
} else if (DestReg == ARM::VPR) {
- assert(ARM::GPRPairRegClass.contains(SrcReg));
+ assert(ARM::GPRRegClass.contains(SrcReg));
BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL));
return;
} else if (SrcReg == ARM::VPR) {
- assert(ARM::GPRPairRegClass.contains(DestReg));
+ assert(ARM::GPRRegClass.contains(DestReg));
BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL));
return;
} else if (DestReg == ARM::FPSCR_NZCV) {
- assert(ARM::GPRPairRegClass.contains(SrcReg));
+ assert(ARM::GPRRegClass.contains(SrcReg));
BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL));
return;
} else if (SrcReg == ARM::FPSCR_NZCV) {
- assert(ARM::GPRPairRegClass.contains(DestReg));
+ assert(ARM::GPRRegClass.contains(DestReg));
BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL));
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