| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ARMBaseInstrInfo getOperandLatency - silence static analyzer dyn_cast<> null ... | Simon Pilgrim | 2019-09-26 | 1 | -2/+2 |
| * | [ARM] Prevent generating NEON stack accesses under MVE. | David Green | 2019-09-09 | 1 | -4/+8 |
| * | [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia... | David Green | 2019-09-03 | 1 | -0/+47 |
| * | [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions. | David Green | 2019-09-03 | 1 | -1/+5 |
| * | Bug fix on function epilog optimization (ARM backend) | Oliver Stannard | 2019-09-03 | 1 | -2/+3 |
| * | Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM | Daniel Sanders | 2019-08-15 | 1 | -42/+42 |
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -13/+12 |
| * | [ARM] Lower "(x<<c) > 0x80000000U" to "lsls" on Thumb1. | Eli Friedman | 2019-07-31 | 1 | -0/+1 |
| * | [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases. | Simon Tatham | 2019-06-27 | 1 | -4/+4 |
| * | [ARM] Code-generation infrastructure for MVE. | Simon Tatham | 2019-06-25 | 1 | -10/+106 |
| * | [ARM] Add MVE vector load/store instructions. | Simon Tatham | 2019-06-25 | 1 | -1/+4 |
| * | [ARM] Comply with rules on ARMv8-A thumb mode partial deprecation of IT. | Huihui Zhang | 2019-06-18 | 1 | -5/+5 |
| * | [ARM] Add the non-MVE instructions in Arm v8.1-M. | Simon Tatham | 2019-06-11 | 1 | -0/+6 |
| * | [ARM] Replace fp-only-sp and d16 with fp64 and d32. | Simon Tatham | 2019-05-28 | 1 | -4/+5 |
| * | [ARM] additionally check for ARM::INLINEASM_BR w/ ARM::INLINEASM | Nick Desaulniers | 2019-05-24 | 1 | -10/+10 |
| * | [ARM] Update check for CBZ in Ifcvt | David Green | 2019-04-23 | 1 | -13/+45 |
| * | [ARM] Don't replicate instructions in Ifcvt at minsize | David Green | 2019-04-23 | 1 | -0/+9 |
| * | [IR] Refactor attribute methods in Function class (NFC) | Evandro Menezes | 2019-04-04 | 1 | -3/+3 |
| * | [ARM] Don't try to create "push {r12, lr}" in Thumb1 at -Oz. | Eli Friedman | 2019-04-01 | 1 | -0/+2 |
| * | [ARM] Don't confuse the scheduler for very large VLDMDIA etc. | Eli Friedman | 2019-03-27 | 1 | -1/+6 |
| * | [ARM] Add missing memory operands to a bunch of instructions. | Eli Friedman | 2019-03-25 | 1 | -2/+4 |
| * | [ARM] Don't form "ands" when it isn't scheduled correctly. | Eli Friedman | 2019-03-22 | 1 | -1/+9 |
| * | [ARM] Add MachineVerifier logic for some Thumb1 instructions. | Eli Friedman | 2019-03-15 | 1 | -0/+25 |
| * | [ARM] Add some more missing T1 opcodes for the peephole optimisier | David Green | 2019-02-25 | 1 | -12/+24 |
| * | [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs | David Green | 2019-02-22 | 1 | -11/+54 |
| * | Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole optim... | David Green | 2019-02-21 | 1 | -54/+12 |
| * | [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs | David Green | 2019-02-21 | 1 | -12/+54 |
| * | [ARM] Ensure we update the correct flags in the peephole optimiser | David Green | 2019-02-14 | 1 | -2/+5 |
| * | [ARM] Add OptMinSize to ARMSubtarget | Sam Parker | 2019-02-08 | 1 | -1/+1 |
| * | [ARM] Reformat isRedundantFlagInstr for D57833. NFC | David Green | 2019-02-07 | 1 | -8/+4 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [ARM] Add missing pseudo-instruction for Thumb1 RSBS. | Eli Friedman | 2018-10-31 | 1 | -0/+1 |
| * | [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. | Eli Friedman | 2018-10-26 | 1 | -0/+2 |
| * | [ARM] Account for implicit IT when calculating inline asm size | Peter Smith | 2018-10-08 | 1 | -2/+6 |
| * | X86, AArch64, ARM: Do not attach debug location to spill/reload instructions | Matthias Braun | 2018-10-05 | 1 | -15/+15 |
| * | Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instr... | Matt Morehouse | 2018-10-02 | 1 | -15/+15 |
| * | X86, AArch64, ARM: Do not attach debug location to spill/reload instructions | Matthias Braun | 2018-10-01 | 1 | -15/+15 |
| * | llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) | Fangrui Song | 2018-09-27 | 1 | -3/+2 |
| * | Remove FrameAccess struct from hasLoadFromStackSlot | Sander de Smalen | 2018-09-05 | 1 | -4/+8 |
| * | Extend hasStoreToStackSlot with list of FI accesses. | Sander de Smalen | 2018-09-03 | 1 | -4/+12 |
| * | [MinGW] [ARM] Add stubs for potential automatic dllimported variables | Martin Storsjo | 2018-08-31 | 1 | -0/+1 |
| * | Make TargetInstrInfo::isCopyInstr return true for regular COPY-instructions | Alexander Ivchenko | 2018-08-30 | 1 | -3/+3 |
| * | [ARM] Move machine operand target flags to ARMBaseInstrInfo | Martin Storsjo | 2018-08-22 | 1 | -0/+28 |
| * | [MI] Change the array of `MachineMemOperand` pointers to be | Chandler Carruth | 2018-08-16 | 1 | -8/+7 |
| * | [NEON] Support vldNq intrinsics in AArch32 (LLVM part) | Ivan A. Kosarev | 2018-06-27 | 1 | -0/+18 |
| * | Change TII isCopyInstr way of returning arguments(NFC) | Petar Jovanovic | 2018-06-06 | 1 | -4/+5 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)" | Ivan A. Kosarev | 2018-06-02 | 1 | -28/+0 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) | Ivan A. Kosarev | 2018-06-02 | 1 | -0/+28 |
| * | [X86][MIPS][ARM] New machine instruction property 'isMoveReg' | Petar Jovanovic | 2018-05-23 | 1 | -0/+18 |
