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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen2012-08-171-0/+3
| | | | | | | | | PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-171-15/+97
| | | | llvm-svn: 162094
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-161-0/+20
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-161-3/+64
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-151-0/+49
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov2012-08-041-0/+4
| | | | | | | | | stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. llvm-svn: 161300
* Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov2012-08-041-3/+43
| | | | | | | | classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | llvm-svn: 160621
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
| | | | llvm-svn: 160093
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
| | | | | | | | It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. llvm-svn: 160090
* Revert accidental checkin.Andrew Trick2012-07-021-3/+2
| | | | | | My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change. llvm-svn: 159548
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-021-10/+11
| | | | | | Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
* ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren2012-06-291-80/+73
| | | | | | | | Use getUniqueVRegDef. Replace a loop with existing interfaces: modifiesRegister and readsRegister. Factor out code into inline functions and simplify the code. llvm-svn: 159470
* Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren2012-06-291-14/+21
| | | | | | instructions with two register operands. llvm-svn: 159465
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-9/+9
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. llvm-svn: 159411
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-9/+9
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 llvm-svn: 159236
* ARM: update peephole optimization.Manman Ren2012-06-251-2/+18
| | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 llvm-svn: 159166
* ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick2012-06-221-5/+9
| | | | | | | | | | This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 llvm-svn: 158960
* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+1
| | | | | | | | Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-1/+2
| | | | llvm-svn: 158164
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
| | | | | | Match expectations of the new latency API. Cleanup and make the logic consistent. llvm-svn: 158163
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
| | | | llvm-svn: 158162
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
| | | | llvm-svn: 158161
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-8/+11
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* Mark a static table as const. Shrink opcode size in static tables to ↵Craig Topper2012-05-241-14/+9
| | | | | | uint16_t. Simplify loop iterating over one of those tables. No functional change intended. llvm-svn: 157367
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-27/+119
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-118/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-27/+118
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.Jakob Stoklund Olesen2012-04-041-0/+23
| | | | | | | | | | A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
| | | | | | | | | | | | | ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> llvm-svn: 153686
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-281-2/+2
| | | | | | | | | The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. llvm-svn: 153603
* ARM has a peephole optimization which looks for a def / use pair. The defEvan Cheng2012-03-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | produces a 32-bit immediate which is consumed by the use. It tries to fold the immediate by breaking it into two parts and fold them into the immmediate fields of two uses. e.g movw r2, #40885 movt r3, #46540 add r0, r0, r3 => add.w r0, r0, #3019898880 add.w r0, r0, #30146560 ; However, this transformation is incorrect if the user produces a flag. e.g. movw r2, #40885 movt r3, #46540 adds r0, r0, r3 => add.w r0, r0, #3019898880 adds.w r0, r0, #30146560 Note the adds.w may not set the carry flag even if the original sequence would. rdar://11116189 llvm-svn: 153484
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+1
| | | | llvm-svn: 153422
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-18/+18
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
| | | | | | | | | | When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. llvm-svn: 152095
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-25/+25
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Use <def,undef> operands when spilling NEON bundles.Jakob Stoklund Olesen2012-03-041-14/+12
| | | | | | | | | | | MachineOperands that define part of a virtual register must have an <undef> flag if they are not intended as read-modify-write operands. The old trick of adding an <imp-def> operand doesn't work any longer. Fixes PR12177. llvm-svn: 152008
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+4
| | | | | | | | | | | | | | Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 llvm-svn: 151673
* Clarify ARM calling conventions.Jakob Stoklund Olesen2012-02-221-0/+2
| | | | llvm-svn: 151113
* Calls don't really change the stack pointer.Jakob Stoklund Olesen2012-02-211-1/+2
| | | | | | | Even if a call instruction has %SP<imp-def> operands, it doesn't change the value of the stack pointer. llvm-svn: 151104
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Handle regmask operands in ARMInstrInfo.Jakob Stoklund Olesen2012-02-171-6/+8
| | | | llvm-svn: 150833
* Fix ARMBaseInstrInfo::getInstrLatency for calls.Jakob Stoklund Olesen2012-02-171-1/+1
| | | | | | Calls always clobber CPSR. llvm-svn: 150831
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-3/+1
| | | | llvm-svn: 149961
* DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng2012-02-051-1/+1
| | | | llvm-svn: 149846
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-85/+81
| | | | llvm-svn: 148578
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-2/+3
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
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