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path: root/llvm/lib/Target/AMDGPU/VOP2Instructions.td
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* AMDGPU/GlobalISel: Fix import of zext of s16 op patternsMatt Arsenault2020-01-091-3/+3
* AMDGPU: Apply i16 add->sub pattern with zext to i32Matt Arsenault2020-01-071-8/+15
* AMDGPU: Fix misleading, misplaced end block commentsMatt Arsenault2020-01-071-2/+2
* AMDGPU/GlobalISel: Select mul24 intrinsicsMatt Arsenault2019-12-301-2/+2
* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-041-5/+5
* [AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32Dmitry Preobrazhensky2019-10-181-52/+77
* [AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwaDmitry Preobrazhensky2019-10-181-1/+1
* [AMDGPU] Supress unused sdwa insts generationStanislav Mekhanoshin2019-10-161-23/+36
* [AMDGPU] link dpp pseudos and real instructions on gfx10Stanislav Mekhanoshin2019-10-111-12/+17
* AMDGPU: Fix i16 arithmetic pattern redundancyMatt Arsenault2019-10-081-78/+23
* [AMDGPU] Disable unused gfx10 dpp instructionsStanislav Mekhanoshin2019-10-081-0/+6
* AMDGPU/GlobalISel: Fix selection of 16-bit shiftsMatt Arsenault2019-10-071-3/+6
* AMDGPU/GlobalISel: Fix select for v2s16 and/or/xorMatt Arsenault2019-09-301-15/+17
* [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16Tim Renouf2019-09-181-1/+3
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-171-1/+2
* AMDGPU/GlobalISel: Select 16-bit VALU bit opsMatt Arsenault2019-09-131-3/+3
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-131-1/+1
* AMDGPU: Move MnemonicAlias out of instruction def hierarchyMatt Arsenault2019-09-091-3/+3
* AMDGPU/GlobalISel: Select G_ASHRMatt Arsenault2019-07-161-1/+1
* AMDGPU/GlobalISel: Select G_LSHRMatt Arsenault2019-07-161-1/+1
* AMDGPU/GlobalISel: Select G_SHLMatt Arsenault2019-07-161-1/+1
* [AMDGPU] gfx908 dot instruction supportStanislav Mekhanoshin2019-07-111-0/+30
* [AMDGPU] gfx908 v_pk_fmac_f16 supportStanislav Mekhanoshin2019-07-091-2/+8
* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-201-2/+2
* [AMDGPU] Use custom inserter for gfx10 VOP2bStanislav Mekhanoshin2019-06-171-1/+3
* [AMDGPU] gfx1011/gfx1012 targetsStanislav Mekhanoshin2019-06-141-0/+54
* [AMDGPU] gfx1010 base changes for wave32Stanislav Mekhanoshin2019-06-131-0/+35
* [AMDGPU] gfx1010 dpp16 and dpp8Stanislav Mekhanoshin2019-06-121-4/+102
* [AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliasesDmitry Preobrazhensky2019-05-141-1/+6
* AMDGPU: Select VOP3 form of addMatt Arsenault2019-05-081-2/+2
* AMDGPU: Fix a mis-placed bracketChangpeng Fang2019-05-081-1/+1
* AMDGPU: Select VOP3 form of subMatt Arsenault2019-05-031-2/+2
* AMDGPU: Remove redundant patterns for shiftsMatt Arsenault2019-05-031-9/+4
* AMDGPU: Remove redundant patterns for subMatt Arsenault2019-05-031-4/+0
* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-261-1/+1
* [AMDGPU] gfx1010 VOP2 changesStanislav Mekhanoshin2019-04-261-125/+419
* [AMDGPU] gfx1010 VOP1 instructionsStanislav Mekhanoshin2019-04-251-2/+2
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-9/+9
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-9/+6
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-10/+19
* [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf2019-03-181-8/+13
* [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b3...Dmitry Preobrazhensky2019-03-041-2/+2
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-11/+11
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-11/+11
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-4/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-1/+6
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-23/+46
* DAG: Change behavior of fminnum/fmaxnum nodesMatt Arsenault2018-10-221-4/+4
* AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9Konstantin Zhuravlyov2018-09-271-6/+19
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