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path: root/llvm/lib/Target/AMDGPU/VOP2Instructions.td
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* AMDGPU: Split VOP2Inst into VOP2Inst_e32/e64/sdwaKonstantin Zhuravlyov2018-09-271-10/+32
* AMDGPU/NFC: Simplify VOP_MAC_F16/F32Konstantin Zhuravlyov2018-09-271-11/+2
* [AMDGPU] Divergence driven instruction selection. Part 1.Alexander Timofeev2018-09-211-24/+78
* AMDGPU: Fix getInstSizeInBytesNicolai Haehnle2018-08-291-9/+0
* AMDGPU: Improve hack for packing conversion opsMatt Arsenault2018-08-011-5/+5
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-0/+20
* [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32Dmitry Preobrazhensky2018-04-161-1/+23
* AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classesNicolai Haehnle2018-03-261-12/+2
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-4/+9
* AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}Marek Olsak2018-01-311-4/+4
* [AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin2018-01-151-0/+1
* [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32Dmitry Preobrazhensky2017-11-291-9/+14
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-45/+120
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-031-14/+14
* [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky2017-08-161-4/+4
* [AMDGPU] Add pseudo "old" source to all DPP instructionsConnor Abbott2017-08-071-5/+4
* AMDGPU: Add encoding for carryless add/sub instructionsMatt Arsenault2017-07-201-0/+14
* [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if om...Sam Kolton2017-07-181-3/+8
* Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth2017-07-181-8/+3
* [AMDGPU] CodeGen: check dst operand type to determine if omod is supported fo...Sam Kolton2017-07-171-3/+8
* [AMDGPU] SDWA: remove support for VOP2 instructions that have only 64-bit enc...Sam Kolton2017-06-221-11/+15
* [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin2017-06-211-0/+9
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-211-26/+7
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-12/+58
* [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64Dmitry Preobrazhensky2017-05-151-11/+22
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler...Dmitry Preobrazhensky2017-05-101-6/+12
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+2
* [AMDGPU][MC] Fix for Bug 28167 + LIT testsDmitry Preobrazhensky2017-04-051-1/+4
* [AMDGPU][MC] Fix for Bug 30829 + LIT testsDmitry Preobrazhensky2017-03-031-0/+2
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-3/+4
* AMDGPU: Add cvt.pkrtz intrinsicMatt Arsenault2017-02-221-1/+1
* AMDGPU: Fix trailing whitespaceMatt Arsenault2017-02-101-3/+3
* AMDGPU: Undo sub x, c -> add x, -c canonicalizationMatt Arsenault2017-01-301-0/+8
* [AMDGPU] Add subtarget features for SDWA/DPPSam Kolton2017-01-201-4/+4
* [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate...Sam Kolton2017-01-111-4/+4
* [AMDGPU] Assembler: support SDWA and DPP for VOP2b instructionsSam Kolton2016-12-271-1/+26
* AMDGPU: Use i16 for i16 shift amountMatt Arsenault2016-12-221-6/+6
* [AMDGPU] Add pseudo SDWA instructionsSam Kolton2016-12-221-22/+28
* [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwaSam Kolton2016-12-221-4/+11
* AMDGPU: Fix name for v_ashrrev_i16Matt Arsenault2016-12-161-3/+3
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-2/+4
* AMDGPU: Select i16 instructions to VOP3 formsMatt Arsenault2016-12-091-10/+10
* AMDGPU: Fix commuting v_sub_u16Matt Arsenault2016-12-081-1/+1
* AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit instsTom Stellard2016-11-181-3/+14
* AMDGPU/SI: Fix pattern for i16 = sign_extend i1Tom Stellard2016-11-151-1/+5
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-19/+40
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-0/+72
* Revert "AMDGPU: Add VI i16 support"Tom Stellard2016-11-041-72/+0
* AMDGPU: Add VI i16 supportTom Stellard2016-11-031-0/+72
* [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx t...Sam Kolton2016-10-071-0/+1
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