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path: root/llvm/lib/Target/AMDGPU/SOPInstructions.td
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* AMDGPU/GlobalISel: Fix import of s_abs_i32 patternMatt Arsenault2020-01-071-1/+1
* AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.voteMatt Arsenault2020-01-071-2/+2
* AMDGPU: Only allow regs for s_movrel_{b32|b64}Matt Arsenault2020-01-031-2/+13
* [AMDGPU] deduplicate tablegen predicatesStanislav Mekhanoshin2019-11-041-1/+1
* AMDGPU/GlobalISel: Allow selection of scalar min/maxMatt Arsenault2019-09-211-4/+4
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-7/+7
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-7/+7
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-7/+7
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-131-1/+3
* [AMDGPU] Mark s_barrier as having side effects but not accessing memory.Jay Foad2019-09-061-2/+0
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-1/+4
* Revert "[AMDGPU] Use S_DENORM_MODE for gfx10"Dmitri Gribenko2019-08-051-4/+1
* [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-051-1/+4
* AMDGPU: Use tablegen pattern for sendmsg intrinsicsMatt Arsenault2019-08-011-4/+3
* AMDGPU: Redefine setcc condition PatLeafsMatt Arsenault2019-07-191-3/+3
* AMDGPU/GlobalISel: Select G_ASHRMatt Arsenault2019-07-161-2/+2
* AMDGPU/GlobalISel: Select G_LSHRMatt Arsenault2019-07-161-2/+2
* AMDGPU/GlobalISel: Select G_SHLMatt Arsenault2019-07-161-2/+2
* AMDGPU: s_waitcnt field should be treated as unsignedMatt Arsenault2019-07-111-1/+1
* [AMDGPU] Created a sub-register class for the return address operand in the r...Christudasan Devadasan2019-07-091-3/+3
* AMDGPU: Move waitcnt intrinsic to instruction definition patternMatt Arsenault2019-07-081-12/+2
* [AMDGPU] Fix for branch offset hardware workaroundRyan Taylor2019-06-261-15/+48
* [AMDGPU] gfx10 wave32 patternsStanislav Mekhanoshin2019-06-181-3/+15
* AMDGPU: Set isTrap on S_TRAPMatt Arsenault2019-06-141-1/+4
* AMDGPU: Fix printing trailing whitespace after s_endpgmMatt Arsenault2019-06-141-1/+1
* [AMDGPU] gfx1010 base changes for wave32Stanislav Mekhanoshin2019-06-131-0/+32
* AMDGPU: Temporary drop s_mul_hi_i/u32 patternsKonstantin Zhuravlyov2019-05-281-6/+2
* [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_forkDmitry Preobrazhensky2019-05-171-2/+2
* [AMDGPU] gfx1010 SOP instructionsStanislav Mekhanoshin2019-04-241-131/+305
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-3/+3
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-17/+16
* [AMDGPU] Enable code selection using `s_mul_hi_u32`/`s_mul_hi_i32`.Michael Liao2019-03-181-2/+6
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-121-3/+6
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-0/+1
* AMDGPU: Correct definitions for bitset instructionsMatt Arsenault2019-02-251-12/+18
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-12/+12
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-12/+12
* AMDGPU: Remove GCN features and predicatesMatt Arsenault2019-02-081-4/+0
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructionsDmitry Preobrazhensky2019-01-181-0/+2
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-291-8/+37
* [AMDGPU] Divergence driven instruction selection. Shift operations.Alexander Timofeev2018-10-011-3/+3
* [AMDGPU] Divergence driven instruction selection. Part 1.Alexander Timofeev2018-09-211-18/+27
* [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32Dmitry Preobrazhensky2018-04-091-0/+21
* [AMDGPU][MC][GFX9] Added s_call_b64Dmitry Preobrazhensky2018-04-061-0/+12
* [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_doneDmitry Preobrazhensky2018-04-061-0/+7
* [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*Dmitry Preobrazhensky2018-04-061-0/+21
* AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classesNicolai Haehnle2018-03-261-18/+20
* AMDGPU: Add llvm.amdgcn.wqm.vote intrinsicMarek Olsak2017-10-241-1/+3
* Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.Wei Ding2017-10-121-2/+3
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