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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-01 18:27:11 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-01 18:27:11 +0000 |
| commit | aff2995f46ec2a38dffcdb3ad5a9cd02197ca7f9 (patch) | |
| tree | e8e40820888a52a3c427735476d292a787c7c6e3 /llvm/lib/Target/AMDGPU/SOPInstructions.td | |
| parent | 20b198ec5ea70de87bcfac2d27b6f4be8b41b986 (diff) | |
| download | bcm5719-llvm-aff2995f46ec2a38dffcdb3ad5a9cd02197ca7f9.tar.gz bcm5719-llvm-aff2995f46ec2a38dffcdb3ad5a9cd02197ca7f9.zip | |
AMDGPU: Use tablegen pattern for sendmsg intrinsics
Since this now emits a direct copy to m0, SIFixSGPRCopies has to
handle a physical register.
llvm-svn: 367593
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SOPInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 1a57509f7c2..58b0c4beca2 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1110,12 +1110,11 @@ def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">; let Uses = [EXEC, M0] in { // FIXME: Should this be mayLoad+mayStore? def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16", - [(AMDGPUsendmsg (i32 imm:$simm16))] ->; + [(int_amdgcn_s_sendmsg (i32 imm:$simm16), M0)]>; def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $simm16", - [(AMDGPUsendmsghalt (i32 imm:$simm16))] ->; + [(int_amdgcn_s_sendmsghalt (i32 imm:$simm16), M0)]>; + } // End Uses = [EXEC, M0] def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16"> { |
