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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
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* [AMDGPU] Override PSet for M0Stanislav Mekhanoshin2017-02-101-0/+2
* [AMDGPU] Implement register pressure callbacksStanislav Mekhanoshin2017-02-081-0/+6
* [AMDGPU] Move register related queries to subtarget classKonstantin Zhuravlyov2017-02-081-66/+0
* [AMDGPU] Do not allow register coalescer to create big superregsStanislav Mekhanoshin2017-01-181-0/+7
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-2/+10
* AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objectsMarek Olsak2016-12-091-1/+3
* AMDGPU/SI: Allow using SGPRs 96-101 on VIMarek Olsak2016-12-091-1/+2
* AMDGPU: Properly implement SIRegisterInfo::isFrameOffsetLegal and needsFrameB...Nicolai Haehnle2016-12-081-0/+2
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-251-3/+8
* Revert "AMDGPU: Fix MMO when splitting spill"Marek Olsak2016-11-251-8/+3
* TRI: Add hook to pass scavenger during frame eliminationMatt Arsenault2016-11-241-1/+2
* AMDGPU: Fix MMO when splitting spillMatt Arsenault2016-11-231-3/+8
* AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies passTom Stellard2016-11-161-0/+2
* AMDGPU: Refactor copyPhysRegMatt Arsenault2016-11-071-0/+3
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-261-5/+5
* AMDGPU: Factor SGPR spilling into separate functionsMatt Arsenault2016-10-041-0/+6
* Revert "AMDGPU: Don't use offen if it is 0"Mehdi Amini2016-10-011-5/+5
* AMDGPU: Don't use offen if it is 0Matt Arsenault2016-10-011-5/+5
* Remove unnecessary call to getAllocatableRegClassMatt Arsenault2016-09-071-7/+0
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-14/+64
* AMDGPU: fix mismatch tags, NFCSaleem Abdulrasool2016-08-291-1/+1
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-0/+2
* AMDGPU/SI: Use a better method for determining the largest pressure setsTom Stellard2016-08-261-4/+11
* AMDGPU: Remove custom getSubRegMatt Arsenault2016-08-111-6/+0
* AMDGPU/SI: Don't use reserved VGPRs for SGPR spillingTom Stellard2016-07-281-1/+2
* AMDGPU: Enable trackLivenessAfterRegAllocMatt Arsenault2016-07-111-0/+1
* AMDGPU: Cleanup subtarget handling.Matt Arsenault2016-06-241-6/+7
* AMDGPU/SI: Propagate the Kill flag in storeRegToStackSlot and eliminateFrameI...Changpeng Fang2016-06-161-1/+1
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-0/+2
* AMDGPU: Enable LocalStackSlotAllocation passMatt Arsenault2016-04-161-0/+21
* AMDGPU/SI: Add support for spilling VGPRs without having to scavenge registersTom Stellard2016-04-131-1/+2
* AMDGPU: Cache information about register pressure setsTom Stellard2016-03-231-0/+4
* AMDGPU: Add SIWholeQuadMode passNicolai Haehnle2016-03-211-2/+5
* AMDGPU: R600 code splitting cleanupMatt Arsenault2016-03-111-3/+3
* AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserterTom Stellard2016-03-041-1/+3
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-1/+3
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-111-0/+4
* AMDGPU/SI: Add SI Machine SchedulerNicolai Haehnle2016-01-131-0/+6
* AMDGPU: Optimize VOP2 operand legalizationMatt Arsenault2015-12-011-0/+7
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-0/+9
* AMDGPU: Rename enums to be consistent with HSA code object terminologyMatt Arsenault2015-11-301-10/+12
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-261-0/+1
* Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard2015-11-121-0/+7
* AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault2015-11-111-7/+0
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-061-0/+7
* AMDGPU/SI: Re-order PreloadedValue enum and number entries based on init orderTom Stellard2015-10-011-9/+12
* AMDGPU: Don't handle invalid reg classes in helper functionsMatt Arsenault2015-09-261-6/+0
* Introduce target hook for optimizing register copiesMatt Arsenault2015-09-241-0/+5
* AMDGPU: Remove dead codeMatt Arsenault2015-09-191-4/+0
* AMDGPU: Make sure to reserve super registersMatt Arsenault2015-08-261-0/+3
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