bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	AMDGPU: Fix adding redundant m0 uses	Matt Arsenault	2015-10-21	1	-2/+0
\| \| \| \| \| \|	BuildMI already adds these since they are defined correctly now. llvm-svn: 250961
*	AMDGPU: Add MachineInstr overloads for instruction format tests	Matt Arsenault	2015-10-20	1	-2/+2
\| \| \| \|	llvm-svn: 250797
*	AMDGPU: Use explicit register size indirect pseudos	Matt Arsenault	2015-10-07	1	-1/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This stops using an unknown reg class operand. Currently build_vector selection has a broken looking check where it tries to use a VGPR reg class and an SGPR one if it sees an SGPR use. With the source operand has an explicit VGPR class, illegal copies will be inserted that SIFixSGPRCopies will take care of normally later, which will allow removing the weird check of build_vector users. Without this, when removed v_movrels_b32 would still be emitted even though all of the values were only stored in SGPRs. llvm-svn: 249494
*	AMDGPU: Fix recomputing dominator tree unnecessarily	Matt Arsenault	2015-09-25	1	-0/+4
\| \| \| \| \| \| \|	SIFixSGPRCopies does not modify the CFG, but this was being recomputed before running SIFoldOperands. llvm-svn: 248587
*	AMDGPU/SI: Remove VCCReg	Matt Arsenault	2015-08-08	1	-4/+4
\| \| \| \|	llvm-svn: 244380
*	AMDGPU/SI: Remove EXECReg	Matt Arsenault	2015-08-05	1	-8/+4
\| \| \| \| \| \|	For the same reasons as the other physical registers. llvm-svn: 244062
*	R600 -> AMDGPU rename	Tom Stellard	2015-06-13	1	-0/+605
	llvm-svn: 239657