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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-08 00:41:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-08-08 00:41:48 +0000 |
| commit | 4635915504b7f998962f1cb96ea16d2f2996bd47 (patch) | |
| tree | df3100a367e4749a11d734979ff73694f3bc2a08 /llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | |
| parent | 6942d1a034ca52cb5f18f69a646b042413b400c0 (diff) | |
| download | bcm5719-llvm-4635915504b7f998962f1cb96ea16d2f2996bd47.tar.gz bcm5719-llvm-4635915504b7f998962f1cb96ea16d2f2996bd47.zip | |
AMDGPU/SI: Remove VCCReg
llvm-svn: 244380
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 1d6627fb18a..d68eba25993 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -313,7 +313,7 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) { .addImm(0); } } else { - BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC) + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32)) .addImm(0) .addOperand(Op); } @@ -359,9 +359,9 @@ void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel, int .addReg(AMDGPU::VCC_LO); // Compare the just read M0 value to all possible Idx values - BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC) - .addReg(AMDGPU::M0) - .addReg(Idx); + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32)) + .addReg(AMDGPU::M0) + .addReg(Idx); // Update EXEC, save the original EXEC value to VCC BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC) |
