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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-261-0/+11
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-4/+8
* AMDGPU: Make exec mask optimzations more resistant to block splitsMatt Arsenault2019-03-281-0/+4
* [AMDGPU] Fix SGPR fixing through SCC chainingMichael Liao2019-03-151-3/+3
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-02-081-0/+6
* [AMDGPU] Fix a weird WWM intrinsic issue.Neil Henning2019-01-291-4/+0
* [AMDGPU] Fixed hazard recognizer to walk predecessorsStanislav Mekhanoshin2019-01-211-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-0/+2
* Revert "[AMDGPU] Fix DPP combiner"Valery Pykhtin2019-01-091-6/+0
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-01-091-0/+6
* [AMDGPU] Add new Mode Register passTim Corringham2018-12-101-0/+8
* [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XORGraham Sellers2018-12-011-0/+3
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-2/+0
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-1/+31
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-291-0/+8
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-5/+4
* [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman2018-11-161-0/+3
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-0/+2
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-10-171-2/+0
* [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructionsScott Linder2018-10-081-11/+21
* [AMDGPU] Assert in getOpSize() there are no sub-dword subregsStanislav Mekhanoshin2018-10-031-1/+6
* [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregsStanislav Mekhanoshin2018-10-011-0/+5
* [AMDGPU] Preliminary patch for divergence driven instruction selection. Immed...Alexander Timofeev2018-09-111-0/+3
* Revert r341413Scott Linder2018-09-061-6/+0
* [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructionsScott Linder2018-09-041-0/+6
* AMDGPU: Shrink insts to fold immediatesMatt Arsenault2018-08-281-0/+3
* AMDGPU: Move canShrink into TIIMatt Arsenault2018-08-281-0/+3
* [AMDGPU] Add support for multi-dword s.buffer.load intrinsicTim Renouf2018-08-251-0/+2
* [PSV] Update API to be able to use TargetCustom without UB.Marcello Maggioni2018-08-201-1/+1
* AMDGPU: Force skip over s_sendmsg and exp instructionsNicolai Haehnle2018-07-301-0/+3
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-3/+3
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-2/+14
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-211-8/+0
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-12/+1
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-20/+20
* [AMDGPU][MC] Added lds support for MUBUF instructionsDmitry Preobrazhensky2018-02-211-0/+3
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-241-1/+1
* AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang2018-01-181-0/+8
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-3/+4
* AMDGPU: Replace list of SMEM buffer opcodesMatt Arsenault2017-11-171-0/+13
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-151-1/+5
* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-091-0/+4
* AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak2017-10-241-0/+3
* AMDGPU: Fix not accounting for instruction size in bundlesMatt Arsenault2017-10-041-0/+1
* AMDGPU: Start selecting s_xnor_{b32, b64}Konstantin Zhuravlyov2017-09-181-0/+3
* Fix warnings in r313297.Jan Sjodin2017-09-141-2/+2
* Add AddresSpace to PseudoSourceValue.Jan Sjodin2017-09-141-0/+3
* Allow target to decide when to cluster loads/stores in mischedStanislav Mekhanoshin2017-09-131-1/+2
* AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault2017-08-311-2/+14
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