summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALUMarek Olsak2018-02-061-2/+8
* AMDGPU: Fold inline offset for loads properly in moveToVALU on GFX9Marek Olsak2018-01-311-22/+31
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-9/+9
* [AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.Sam Kolton2017-12-041-0/+22
* AMDGPU: Use carry-less adds in FI eliminationMatt Arsenault2017-11-301-1/+4
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-16/+73
* AMDGPU: Consistently check for immediates in SIInstrInfo::FoldImmediateNicolai Haehnle2017-11-281-23/+22
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-151-0/+73
* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-091-2/+32
* AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offsetMarek Olsak2017-10-311-0/+21
* AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak2017-10-241-0/+21
* AMDGPU: Fix not accounting for instruction size in bundlesMatt Arsenault2017-10-041-1/+14
* AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle2017-09-291-7/+16
* AMDGPU: Fix crash on immediate operandMatt Arsenault2017-09-211-1/+5
* AMDGPU: Start selecting s_xnor_{b32, b64}Konstantin Zhuravlyov2017-09-181-0/+37
* Fix warnings in r313297.Jan Sjodin2017-09-141-3/+1
* AMDGPU: Fix violating constant bus restrictionMatt Arsenault2017-09-141-4/+5
* Add AddresSpace to PseudoSourceValue.Jan Sjodin2017-09-141-0/+19
* AMDGPU: Don't spill SP reg like a normal CSRMatt Arsenault2017-09-131-0/+4
* Allow target to decide when to cluster loads/stores in mischedStanislav Mekhanoshin2017-09-131-0/+38
* [AMDGPU] Produce madak and madmk from the two-address passStanislav Mekhanoshin2017-09-111-0/+42
* [AMDGPU] Fix shouldClusterMemOps to process flat loadsStanislav Mekhanoshin2017-09-061-0/+4
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-08-081-25/+47
* [AMDGPU] Implement llvm.amdgcn.set.inactive intrinsicConnor Abbott2017-08-041-0/+22
* [AMDGPU] Add support for Whole Wavefront ModeConnor Abbott2017-08-041-0/+8
* [AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQMConnor Abbott2017-08-041-0/+2
* AMDGPU: Pass special input registers to functionsMatt Arsenault2017-08-031-5/+4
* AMDGPU: Make areMemAccessesTriviallyDisjoint more aware of segment flatMatt Arsenault2017-07-291-1/+1
* AMDGPU: Fix getMemOpBaseRegImmOfs for flat with offsetsMatt Arsenault2017-07-211-3/+13
* Add an ID field to StackObjectsMatt Arsenault2017-07-201-0/+2
* [AMDGPU] Do not insert an instruction into worklist twice in movetovaluAlfred Huang2017-07-141-12/+12
* [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim2017-07-071-0/+2
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+18
* [AMDGPU] SDWA: several fixes for V_CVT and VOPC instructionsSam Kolton2017-06-271-5/+9
* AMDGPU: M0 operands to spill/restore opcodes are deadNicolai Haehnle2017-06-271-2/+2
* [AMDGPU] SDWA: add support for GFX9 in peephole passSam Kolton2017-06-221-4/+4
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-211-2/+69
* AMDGPU: Don't add same implicit use multiple timesMatt Arsenault2017-06-121-4/+2
* AMDGPU: Verify that flat offsets aren't used pre-GFX9Matt Arsenault2017-06-121-2/+11
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU/GlobalISel: Mark 32-bit float constants as legalTom Stellard2017-05-261-0/+4
* AMDGPU: Use appropriate soffset for spillingMatt Arsenault2017-05-171-7/+7
* AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]NAKAMURA Takumi2017-05-161-2/+2
* Re-submit AMDGPUMachineCFGStructurizer.Jan Sjodin2017-05-151-9/+301
* Revert 303091.Jan Sjodin2017-05-151-301/+9
* Add AMDGPUMachineCFGStructurizer.Jan Sjodin2017-05-151-9/+301
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-18/+20
* AMDGPU: Move v_readlane lane select from VGPR to SGPRNicolai Haehnle2017-04-241-0/+13
* AMDGPU: Fix crash when scheduling non-memory SMRD instructionsNicolai Haehnle2017-04-241-0/+5
OpenPOWER on IntegriCloud