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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2017-05-16 04:01:23 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2017-05-16 04:01:23 +0000 |
| commit | 994a43d27a7e844f569816f4947a8c4031f73cbc (patch) | |
| tree | 183325033d7dc2813f6470c57b4cb3b6938cb25b /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | a0a6d59da822a7c250b4980e43e996b4435afd56 (diff) | |
| download | bcm5719-llvm-994a43d27a7e844f569816f4947a8c4031f73cbc.tar.gz bcm5719-llvm-994a43d27a7e844f569816f4947a8c4031f73cbc.zip | |
AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]
llvm-svn: 303137
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index c87b04256f8..065fd09eb35 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -564,8 +564,8 @@ void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB, unsigned TrueReg, unsigned FalseReg) const { MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); - const TargetRegisterClass *RegClass = MRI.getRegClass(DstReg); - assert(RegClass == &AMDGPU::VGPR_32RegClass && "Not a VGPR32 reg"); + assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && + "Not a VGPR32 reg"); if (Cond.size() == 1) { BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) |
