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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-13 23:47:01 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-13 23:47:01 +0000 |
| commit | ecb43ef1bca8bfd8e27b3c65451eee11ef5898f3 (patch) | |
| tree | fb897031081eaf568df542322110f7e0479509ef /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | cc40ef859ad671f20fa3f82ab70c4795c925bb3b (diff) | |
| download | bcm5719-llvm-ecb43ef1bca8bfd8e27b3c65451eee11ef5898f3.tar.gz bcm5719-llvm-ecb43ef1bca8bfd8e27b3c65451eee11ef5898f3.zip | |
AMDGPU: Don't spill SP reg like a normal CSR
llvm-svn: 313217
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 2279afaf89e..73eb3a3b5f6 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -818,6 +818,10 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineFrameInfo &FrameInfo = MF->getFrameInfo(); DebugLoc DL = MBB.findDebugLoc(MI); + assert(SrcReg != MFI->getStackPtrOffsetReg() && + SrcReg != MFI->getFrameOffsetReg() && + SrcReg != MFI->getScratchWaveOffsetReg()); + unsigned Size = FrameInfo.getObjectSize(FrameIndex); unsigned Align = FrameInfo.getObjectAlignment(FrameIndex); MachinePointerInfo PtrInfo |
