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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-26/+34
* [AMDGPU] gfx1010 constant bus limitStanislav Mekhanoshin2019-05-021-22/+82
* [AMDGPU] gfx1010 MIMG implementationStanislav Mekhanoshin2019-05-011-3/+60
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-0/+4
* Revert "AMDGPU: Split block for si_end_cf"Mark Searles2019-04-271-7/+0
* [AMDGPU] gfx1010 VOP3 and VOP3P implementationStanislav Mekhanoshin2019-04-261-0/+2
* [AMDGPU] gfx1010 VOP2 changesStanislav Mekhanoshin2019-04-261-2/+2
* [AMDGPU] Add gfx1010 target definitionsStanislav Mekhanoshin2019-04-241-1/+5
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-14/+14
* AMDGPU: Split block for si_end_cfMatt Arsenault2019-04-031-0/+7
* [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning2019-04-011-3/+14
* AMDGPU: Make exec mask optimzations more resistant to block splitsMatt Arsenault2019-03-281-0/+21
* AMDGPU: Don't hardcode num defs for MUBUF instructionsMatt Arsenault2019-03-271-2/+2
* AMDGPU: Fix areLoadsFromSameBasePtr for DS atomicsMatt Arsenault2019-03-271-4/+11
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+8
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-8/+17
* [AMDGPU] Enable code selection using `s_mul_hi_u32`/`s_mul_hi_i32`.Michael Liao2019-03-181-0/+4
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-4/+9
* [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf2019-03-181-1/+16
* [AMDGPU] Fix SGPR fixing through SCC chainingMichael Liao2019-03-151-9/+15
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-121-3/+7
* AMDGPU: Don't bother checking the chain in areLoadsFromSameBasePtrMatt Arsenault2019-03-081-15/+0
* AMDGPU: Correct DS implementation of areLoadsFromSameBasePtrMatt Arsenault2019-03-081-4/+4
* AMDGPU: Use MachineInstr::mayAlias to replace areMemAccessesTriviallyDisjoint...Changpeng Fang2019-02-181-11/+0
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-02-081-0/+26
* AMDGPU: Don't rematerialize mov with implicit operandsMatt Arsenault2019-02-041-1/+2
* [AMDGPU] Fix a weird WWM intrinsic issue.Neil Henning2019-01-291-13/+17
* AMDGPU: Add DS append/consume intrinsicsMatt Arsenault2019-01-281-0/+5
* [AMDGPU] Fixed hazard recognizer to walk predecessorsStanislav Mekhanoshin2019-01-211-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Remove llvm.SI.load.constMatt Arsenault2019-01-181-1/+0
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-1/+12
* [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard2019-01-141-0/+36
* Revert "[AMDGPU] Fix DPP combiner"Valery Pykhtin2019-01-091-26/+0
* [AMDGPU] Fix DPP combinerValery Pykhtin2019-01-091-0/+26
* [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed PseudosRon Lieberman2018-12-031-0/+4
* [AMDGPU] Split 64-Bit XNOR to 64-Bit NOT/XORGraham Sellers2018-12-011-7/+52
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-178/+7
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-301-0/+81
* Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard2018-11-291-36/+0
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-291-26/+161
* Add support for TFE/LWE in image intrinsicsDavid Stuttard2018-11-291-0/+36
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-32/+45
* AMDGPU: Record SGPR spills when restoring tooMatt Arsenault2018-11-261-1/+3
* AMDGPU: Fix analyzeBranch failing with pseudoterminatorsMatt Arsenault2018-11-161-1/+28
* [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdxStanislav Mekhanoshin2018-11-091-2/+2
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-7/+178
* [AMDGPU] Remove FeatureVGPRSpillingScott Linder2018-10-311-19/+0
* AMDGPU: Use scavengeRegisterBackwardsMatt Arsenault2018-10-301-2/+3
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