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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-27 16:12:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-27 16:12:29 +0000 |
| commit | 28f97f1dbc877ef386c3715cba17d5dcfa748c03 (patch) | |
| tree | d51b366b98c95d86058a10932282f0b014adf17e /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | 733b8571b4a3d432caed5e48c94784f930bc0687 (diff) | |
| download | bcm5719-llvm-28f97f1dbc877ef386c3715cba17d5dcfa748c03.tar.gz bcm5719-llvm-28f97f1dbc877ef386c3715cba17d5dcfa748c03.zip | |
AMDGPU: Don't hardcode num defs for MUBUF instructions
This shouldn't change anything since the no-ret atomics are selected
later.
llvm-svn: 357084
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 6155ad72f4c..7639a3fe138 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -226,8 +226,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, // getNamedOperandIdx returns the index for MachineInstrs. Since they // include the output in the operand list, but SDNodes don't, we need to // subtract the index by one. - --OffIdx0; - --OffIdx1; + OffIdx0 -= get(Opc0).NumDefs; + OffIdx1 -= get(Opc1).NumDefs; SDValue Off0 = Load0->getOperand(OffIdx0); SDValue Off1 = Load1->getOperand(OffIdx1); |
