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| author | Neil Henning <neil.henning@amd.com> | 2019-01-29 14:28:17 +0000 |
|---|---|---|
| committer | Neil Henning <neil.henning@amd.com> | 2019-01-29 14:28:17 +0000 |
| commit | 0799352026a952dbb61017f0b0f0b541c3e10fce (patch) | |
| tree | ffae7df45cf335975f59d06872a122f2ff9c5f4d /llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | |
| parent | ae82599a30be6d82bb18f9bae87acb6e3ae36da5 (diff) | |
| download | bcm5719-llvm-0799352026a952dbb61017f0b0f0b541c3e10fce.tar.gz bcm5719-llvm-0799352026a952dbb61017f0b0f0b541c3e10fce.zip | |
[AMDGPU] Fix a weird WWM intrinsic issue.
I found a really strange WWM issue through a very convoluted shader that
essentially boils down to a bug in SIInstrInfo where canReadVGPR did not
correctly identify that WWM is like a copy and can have a VGPR as its
source.
Differential Revision: https://reviews.llvm.org/D56002
llvm-svn: 352500
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 45687d4486e..b857d9df823 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -3277,18 +3277,6 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, return RI.getRegClass(RCID); } -bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const { - switch (MI.getOpcode()) { - case AMDGPU::COPY: - case AMDGPU::REG_SEQUENCE: - case AMDGPU::PHI: - case AMDGPU::INSERT_SUBREG: - return RI.hasVGPRs(getOpRegClass(MI, 0)); - default: - return RI.hasVGPRs(getOpRegClass(MI, OpNo)); - } -} - void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const { MachineBasicBlock::iterator I = MI; MachineBasicBlock *MBB = MI.getParent(); @@ -4957,7 +4945,23 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist( for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg), E = MRI.use_end(); I != E;) { MachineInstr &UseMI = *I->getParent(); - if (!canReadVGPR(UseMI, I.getOperandNo())) { + + unsigned OpNo = 0; + + switch (UseMI.getOpcode()) { + case AMDGPU::COPY: + case AMDGPU::WQM: + case AMDGPU::WWM: + case AMDGPU::REG_SEQUENCE: + case AMDGPU::PHI: + case AMDGPU::INSERT_SUBREG: + break; + default: + OpNo = I.getOperandNo(); + break; + } + + if (!RI.hasVGPRs(getOpRegClass(UseMI, OpNo))) { Worklist.insert(&UseMI); do { |

