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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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* AMDGPU: Remove dx10-clamp from subtarget featuresMatt Arsenault2019-03-291-5/+18
* [AMDGPU] Use three- and five-dword result type in image opsTim Renouf2019-03-221-9/+6
* [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsicsTim Renouf2019-03-221-15/+48
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+17
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-8/+69
* [AMDGPU] Allow MIMG with no uses in adjustWritemask in iselDavid Stuttard2019-03-201-0/+4
* [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsicsRyan Taylor2019-03-191-1/+112
* [AMDGPU] Ban i8 min3 promotion.Neil Henning2019-03-191-3/+3
* [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf2019-03-181-0/+4
* [AMDGPU] Add an experimental buffer fat pointer address space.Neil Henning2019-03-181-1/+2
* MIR: Allow targets to serialize MachineFunctionInfoMatt Arsenault2019-03-141-5/+14
* IR: Add immarg attributeMatt Arsenault2019-03-121-27/+11
* DAG: Don't try to cluster loads with tied inputsMatt Arsenault2019-03-081-45/+0
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-2/+2
* [AMDGPU] Fixed hang during DAG combineStanislav Mekhanoshin2019-02-261-1/+2
* AMDGPU: Remove debugger related subtarget featuresMatt Arsenault2019-02-211-32/+0
* [AMDGPU] fix commuted case of sub combineStanislav Mekhanoshin2019-02-211-5/+1
* [AMDGPU] Ressociate 'add (add x, y), z' to use SALUStanislav Mekhanoshin2019-02-141-0/+43
* [AMDGPU] Split dot-insts featureStanislav Mekhanoshin2019-02-091-1/+1
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
* AMDGPU/GlobalISel: Legalize addrspacecastMatt Arsenault2019-02-081-1/+2
* [AMDGPU] Consider XOR in waterfall loop as a terminatorScott Linder2019-02-051-1/+1
* [AMDGPU] Support emitting GOT relocations for function callsScott Linder2019-02-041-23/+13
* [AMDGPU] Fix for vector element insertionTim Corringham2019-02-011-5/+5
* AMDGPU: Add DS append/consume intrinsicsMatt Arsenault2019-01-281-1/+15
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-281-0/+53
* Codegen support for atomicrmw fadd/fsubMatt Arsenault2019-01-221-6/+42
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Remove llvm.SI.load.constMatt Arsenault2019-01-181-7/+0
* AMDGPU: Adjust the chain for loads writing to the HI part of a register.Changpeng Fang2019-01-161-0/+45
* AMDGPU: Add llvm.amdgcn.ds.ordered.add & swapMarek Olsak2019-01-161-0/+61
* AMDGPU: Add a fast path for icmp.i1(src, false, NE)Marek Olsak2019-01-151-0/+5
* [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard2019-01-141-53/+289
* [AMDGPU] Separate feature dot-instsStanislav Mekhanoshin2019-01-101-1/+1
* Remove check for single use in ShrinkDemandedConstantStanislav Mekhanoshin2019-01-091-2/+1
* [AMDGPU] Handle OR as operand of raw load/storePiotr Sobczak2019-01-021-4/+6
* Fix unused variable warning. NFCI.Simon Pilgrim2018-12-071-2/+2
* AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.loadMatt Arsenault2018-12-071-5/+6
* AMDGPU: Remove llvm.SI.tbuffer.storeMatt Arsenault2018-12-071-49/+0
* AMDGPU: Remove llvm.AMDGPU.killMatt Arsenault2018-12-071-15/+2
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-33/+74
* AMDGPU: Fix various issues around the VirtReg2Value mappingNicolai Haehnle2018-11-301-29/+36
* Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard2018-11-291-289/+53
* Fix: Add support for TFE/LWE in image intrinsicDavid Stuttard2018-11-291-2/+1
* Add support for TFE/LWE in image intrinsicsDavid Stuttard2018-11-291-53/+290
* [AMDGPU] Disable DAG combine at -O0Stanislav Mekhanoshin2018-11-271-6/+5
* [AMDGPU] Fix -Wunused-variableFangrui Song2018-11-191-1/+0
* [AMDGPU] Convert insert_vector_elt into set of selectsStanislav Mekhanoshin2018-11-191-0/+40
* [AMDGPU] combine extractelement into several selectsStanislav Mekhanoshin2018-11-131-4/+26
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-74/+33
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