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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-07 17:46:16 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-12-07 17:46:16 +0000 |
commit | aa9bcd56b13f07468a1de0b46d374b82fb8a1f5e (patch) | |
tree | 7a8073fab1f4e3412a89bf32cb991d0062bd8700 /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
parent | 30388d6485e8d2afd48cabffc64e921d0585e8ba (diff) | |
download | bcm5719-llvm-aa9bcd56b13f07468a1de0b46d374b82fb8a1f5e.tar.gz bcm5719-llvm-aa9bcd56b13f07468a1de0b46d374b82fb8a1f5e.zip |
AMDGPU: Remove llvm.AMDGPU.kill
This is the last of the old AMDGPU intrinsics.
llvm-svn: 348615
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index fd4b1f361cd..ca9866f441c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5065,7 +5065,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32, SDLoc(DAG.getEntryNode()), MFI->getArgInfo().WorkItemIDZ); - case AMDGPUIntrinsic::SI_load_const: { + case SIIntrinsic::SI_load_const: { SDValue Load = lowerSBuffer(MVT::i32, DL, Op.getOperand(1), Op.getOperand(2), DAG.getTargetConstant(0, DL, MVT::i1), DAG); @@ -5808,19 +5808,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, return DAG.getNode(AMDGPUISD::INIT_EXEC_FROM_INPUT, DL, MVT::Other, Chain, Op.getOperand(2), Op.getOperand(3)); } - case AMDGPUIntrinsic::AMDGPU_kill: { - SDValue Src = Op.getOperand(2); - if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Src)) { - if (!K->isNegative()) - return Chain; - - SDValue NegOne = DAG.getTargetConstant(FloatToBits(-1.0f), DL, MVT::i32); - return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, NegOne); - } - - SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src); - return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast); - } case Intrinsic::amdgcn_s_barrier: { if (getTargetMachine().getOptLevel() > CodeGenOpt::None) { const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); @@ -5831,7 +5818,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, } return SDValue(); }; - case AMDGPUIntrinsic::SI_tbuffer_store: { + case SIIntrinsic::SI_tbuffer_store: { // Extract vindex and voffset from vaddr as appropriate const ConstantSDNode *OffEn = cast<ConstantSDNode>(Op.getOperand(10)); |