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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-12-07 18:03:47 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-12-07 18:03:47 +0000
commitca8eb0b6729c118bc3e872d76fea09e12e645c7e (patch)
treefda4f77ba1b6c3e812ae7dc93ff59d28d005c43d /llvm/lib/Target/AMDGPU/SIISelLowering.cpp
parent03872dd6c886aed612be531beb3e075ac87cdf9d (diff)
downloadbcm5719-llvm-ca8eb0b6729c118bc3e872d76fea09e12e645c7e.tar.gz
bcm5719-llvm-ca8eb0b6729c118bc3e872d76fea09e12e645c7e.zip
AMDGPU: Remove llvm.SI.tbuffer.store
llvm-svn: 348619
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp49
1 files changed, 0 insertions, 49 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ca9866f441c..a98183b28bb 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5818,55 +5818,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
}
return SDValue();
};
- case SIIntrinsic::SI_tbuffer_store: {
-
- // Extract vindex and voffset from vaddr as appropriate
- const ConstantSDNode *OffEn = cast<ConstantSDNode>(Op.getOperand(10));
- const ConstantSDNode *IdxEn = cast<ConstantSDNode>(Op.getOperand(11));
- SDValue VAddr = Op.getOperand(5);
-
- SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32);
-
- assert(!(OffEn->isOne() && IdxEn->isOne()) &&
- "Legacy intrinsic doesn't support both offset and index - use new version");
-
- SDValue VIndex = IdxEn->isOne() ? VAddr : Zero;
- SDValue VOffset = OffEn->isOne() ? VAddr : Zero;
-
- // Deal with the vec-3 case
- const ConstantSDNode *NumChannels = cast<ConstantSDNode>(Op.getOperand(4));
- auto Opcode = NumChannels->getZExtValue() == 3 ?
- AMDGPUISD::TBUFFER_STORE_FORMAT_X3 : AMDGPUISD::TBUFFER_STORE_FORMAT;
-
- unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
- unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
- unsigned Glc = cast<ConstantSDNode>(Op.getOperand(12))->getZExtValue();
- unsigned Slc = cast<ConstantSDNode>(Op.getOperand(13))->getZExtValue();
- SDValue Ops[] = {
- Chain,
- Op.getOperand(3), // vdata
- Op.getOperand(2), // rsrc
- VIndex,
- VOffset,
- Op.getOperand(6), // soffset
- Op.getOperand(7), // inst_offset
- DAG.getConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
- DAG.getConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
- DAG.getConstant(IdxEn->isOne(), DL, MVT::i1), // idxen
- };
-
- assert((cast<ConstantSDNode>(Op.getOperand(14)))->getZExtValue() == 0 &&
- "Value of tfe other than zero is unsupported");
-
- EVT VT = Op.getOperand(3).getValueType();
- MachineMemOperand *MMO = MF.getMachineMemOperand(
- MachinePointerInfo(),
- MachineMemOperand::MOStore,
- VT.getStoreSize(), 4);
- return DAG.getMemIntrinsicNode(Opcode, DL,
- Op->getVTList(), Ops, VT, MMO);
- }
-
case Intrinsic::amdgcn_tbuffer_store: {
SDValue VData = Op.getOperand(2);
bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
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