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path: root/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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* AMDGPU: Support shrinking add with FI in SIFoldOperandsMatt Arsenault2019-05-031-35/+37
* AMDGPU: Replace shrunk instruction with dummy implicit_defMatt Arsenault2019-05-031-4/+8
* AMDGPU: Fix incorrect commute with sub when folding immediatesMatt Arsenault2019-05-031-1/+4
* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-3/+10
* [AMDGPU] Fix an issue in `op_sel_hi` skipping.Michael Liao2019-04-221-7/+16
* AMDGPU: Remove dx10-clamp from subtarget featuresMatt Arsenault2019-03-291-1/+2
* [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf2019-03-181-3/+12
* [AMDGPU] Silence gcc 7 warningsStanislav Mekhanoshin2019-03-131-1/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Fix scalar operand folding bug that causes SHOC performance regression.Alexander Timofeev2019-01-031-3/+7
* [AMDGPU] Fold copy (copy vgpr)Stanislav Mekhanoshin2018-09-271-0/+14
* [AMDGPU] Preliminary patch for divergence driven instruction selection. Opera...Alexander Timofeev2018-08-301-2/+25
* [AMDGPU] Fix -Wunused-variable when -DLLVM_ENABLE_ASSERTIONS=offFangrui Song2018-08-281-2/+1
* AMDGPU: Force shrinking of add/sub even if the carry is usedMatt Arsenault2018-08-281-5/+8
* AMDGPU: Shrink insts to fold immediatesMatt Arsenault2018-08-281-7/+81
* AMDGPU: Check NSZ MI flag when folding omodMatt Arsenault2018-08-121-4/+6
* AMDGPU: Fold v_lshl_or_b32 with 0 src0Matt Arsenault2018-08-061-0/+13
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-2/+2
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-281-2/+2
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-7/+9
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-5/+13
* [AMDGPU] Truncate packed inline constantStanislav Mekhanoshin2018-04-241-1/+1
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-191-2/+12
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-171-0/+19
* AMDGPU: Fix crash when constant folding with physreg operandMatt Arsenault2018-03-101-1/+2
* AMDGPU: Don't crash when trying to fold implicit operandsMatt Arsenault2018-02-081-0/+1
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-1/+1
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-131-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-2/+2
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-4/+4
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-2/+2
* Remove unused variablesVitaly Buka2017-10-151-1/+1
* AMDGPU: Add comment about clampsMatt Arsenault2017-10-051-0/+2
* AMDGPU: Do not fold clamp instructions when sources are differentMatt Arsenault2017-10-051-0/+1
* AMDGPU: Start selecting v_mad_mixhi_f16Matt Arsenault2017-09-201-0/+1
* AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault2017-08-311-5/+18
* AMDGPU: Fix crash when folding immediates into multiple usesNicolai Haehnle2017-07-181-0/+1
* [AMDGPU] Fix -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim2017-07-071-0/+1
* AMDGPU: Do operand folding in program orderMatt Arsenault2017-06-201-5/+3
* AMDGPU: Preserve undef when folding register operandsMatt Arsenault2017-06-201-0/+2
* AMDGPU: Fix crash with undef vreg input operandMatt Arsenault2017-06-201-1/+1
* [AMDGPU] Fix SIFoldOperands crash with clampStanislav Mekhanoshin2017-06-051-1/+2
* [AMDGPU] Preserve operand order in SIFoldOperandsStanislav Mekhanoshin2017-06-031-3/+18
* [AMDGPU] Allow SDWA in instructions with immediates and SGPRsStanislav Mekhanoshin2017-05-301-3/+4
* [AMDGPU] SDWA Peephole: improve search for immediates in SDWA patternsSam Kolton2017-03-311-22/+1
* [AMDGPU] Fold V_CNDMASK with identical source operandsStanislav Mekhanoshin2017-03-241-0/+29
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-6/+8
* AMDGPU: Fold omod into instructionsMatt Arsenault2017-02-271-5/+139
* AMDGPU: Use clamp with f64Matt Arsenault2017-02-221-1/+2
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