diff options
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
| commit | 9d7bb0cb408e993181fc1b28986c7eb3495f28b9 (patch) | |
| tree | 117b65c086189d16940bde7b400f0fd4312d98de /llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | |
| parent | 2803bfaf001241a98608c263a824a5f5ec542511 (diff) | |
| download | bcm5719-llvm-9d7bb0cb408e993181fc1b28986c7eb3495f28b9.tar.gz bcm5719-llvm-9d7bb0cb408e993181fc1b28986c7eb3495f28b9.zip | |
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
llvm-svn: 319187
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFoldOperands.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 0fa6712527f..2c52e16892c 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -971,9 +971,9 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { // Prevent folding operands backwards in the function. For example, // the COPY opcode must not be replaced by 1 in this example: // - // %vreg3<def> = COPY %VGPR0; VGPR_32:%vreg3 + // %vreg3<def> = COPY %vgpr0; VGPR_32:%vreg3 // ... - // %VGPR0<def> = V_MOV_B32_e32 1, %EXEC<imp-use> + // %vgpr0<def> = V_MOV_B32_e32 1, %exec<imp-use> MachineOperand &Dst = MI.getOperand(0); if (Dst.isReg() && !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) |
