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path: root/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
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* Sink all InitializePasses.h includesReid Kleckner2019-11-131-1/+2
* [AMDGPU] move PHI nodes to AGPR classStanislav Mekhanoshin2019-10-181-5/+16
* [AMDGPU] Fix-up cases where writelane has 2 SGPR operandsDavid Stuttard2019-10-161-0/+61
* AMDGPU: Fix infinite searches in SIFixSGPRCopiesAustin Kerbow2019-10-151-1/+5
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-121/+89
* AMDGPU: Fix typosMatt Arsenault2019-10-091-2/+2
* AMDGPU: Fix bug in r371671 on some builds.Austin Kerbow2019-09-121-2/+5
* AMDGPU: Move m0 initializations earlierAustin Kerbow2019-09-111-4/+38
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-12/+12
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-14/+12
* AMDGPU: Use tablegen pattern for sendmsg intrinsicsMatt Arsenault2019-08-011-4/+20
* [AMDGPU] Add llvm.amdgcn.softwqm intrinsicCarl Ritson2019-07-261-0/+1
* [AMDGPU] Enable merging m0 initializations.Austin Kerbow2019-07-151-15/+32
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-111-7/+21
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-66/+103
* [AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.Michael Liao2019-05-281-1/+5
* [AMDGPU] Fix for the address sanitizer failure. Fixing typoAlexander Timofeev2019-05-271-1/+1
* [AMDGPU] Fix for the address sanitizer failure caused by the ifollowing c...Alexander Timofeev2019-05-271-1/+3
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-104/+62
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-62/+80
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-80/+62
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle2018-10-311-2/+4
* AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle2018-10-311-2/+0
* [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructionsScott Linder2018-10-081-5/+5
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-1/+1
* AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard2018-05-221-0/+1
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-15/+17
* [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev2018-04-251-64/+15
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-11/+14
* [AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev2017-12-011-15/+64
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-17/+17
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use war...Eugene Zelenko2017-08-081-19/+32
* [AMDGPU] Add support for Whole Wavefront ModeConnor Abbott2017-08-041-1/+2
* [AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQMConnor Abbott2017-08-041-1/+5
* AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when ...Changpeng Fang2017-08-031-3/+3
* [AMDGPU] Eliminate SGPR to VGPR copy when possibleStanislav Mekhanoshin2017-06-201-0/+30
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault2017-04-291-4/+9
* [AMDGPU] Merge M0 initializationsStanislav Mekhanoshin2017-04-241-9/+176
* AMDGPU : Fix common dominator of two incoming blocks terminates with uniform ...Wei Ding2017-04-121-2/+24
* AMDGPU: Fix folding reg_sequence into copy to phys regMatt Arsenault2017-04-111-0/+4
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-2/+3
* AMDGPU/SI: Don't move copies of immediates to the VALUTom Stellard2016-12-061-1/+43
* AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar br...Tom Stellard2016-11-291-8/+38
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-111-24/+44
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-3/+1
* Revert "AMDGPU: Remove unused control flow intrinsic"Matt Arsenault2016-07-091-0/+1
* AMDGPU: Remove unused control flow intrinsicMatt Arsenault2016-07-081-1/+0
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