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path: root/llvm/lib/Target/AMDGPU/InstPrinter
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* [AMDGPU] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-114-1837/+0
* [AMDGPU] gfx1010 exp modificationsStanislav Mekhanoshin2019-05-081-1/+3
* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-0/+8
* [AMDGPU] gfx1010 MIMG implementationStanislav Mekhanoshin2019-05-012-2/+20
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-302-3/+18
* [AMDGPU] gfx1010 VOPC implementationStanislav Mekhanoshin2019-04-262-9/+69
* [AMDGPU] gfx1010 sgpr register changesStanislav Mekhanoshin2019-04-241-1/+8
* AMDGPU: Fix printed format of SReg_96Matt Arsenault2019-04-151-0/+3
* fix typo: "\t" => " "Liang Zou2019-03-311-1/+1
* [AMDGPU] Added v5i32 and v5f32 register classesTim Renouf2019-03-221-0/+3
* [AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, priva...Dmitry Preobrazhensky2019-03-201-0/+15
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-122-0/+13
* [AMDGPU] Mark enum types in SIDefines.h as unsignedStanislav Mekhanoshin2019-03-111-1/+1
* [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instruc...Dmitry Preobrazhensky2019-02-271-15/+16
* [AMDGPU][MC] Added support of lds_direct operandDmitry Preobrazhensky2019-02-081-0/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-193-12/+9
* [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operandsDmitry Preobrazhensky2019-01-181-1/+1
* AMDGPU: Re-apply r341982 after fixing the layering issueKonstantin Zhuravlyov2018-09-121-2/+1
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into Targ...Ilya Biryukov2018-09-121-1/+2
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-111-2/+1
* [AMDGPU] Add support for a16 modifiear for gfx9Ryan Taylor2018-08-282-3/+6
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-212-19/+8
* AMDGPU: Separate R600 and GCN TableGen filesTom Stellard2018-06-282-89/+17
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-212-0/+7
* [AMDGPU] Added checks for dpp_ctrl valueStanislav Mekhanoshin2018-05-081-13/+18
* [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP o...Dmitry Preobrazhensky2018-03-162-0/+12
* [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32Stanislav Mekhanoshin2018-01-151-1/+4
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-101-0/+9
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-221-2/+2
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-111-10/+0
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-272-4/+4
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-3/+6
* AMDGPU: Add R600InstPrinter classTom Stellard2017-08-172-108/+250
* [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky2017-08-072-0/+9
* AMDGPU: Remove deadcode from AMDGPUInstPrinterTom Stellard2017-07-292-25/+0
* AMDGPU: Fix allocating pseudo-registersMatt Arsenault2017-07-241-0/+5
* [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky2017-07-212-4/+21
* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-222-0/+22
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-1/+0
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-202-0/+19
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-312-0/+108
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-071-1/+1
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-201-2/+23
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-272-0/+87
* AMDGPU: Change exp with compr bit printingMatt Arsenault2017-02-221-3/+11
* [AMDGPU] Add target information that is required by tools to metadataKonstantin Zhuravlyov2017-02-081-5/+6
* AMDGPU: Change vintrp printingMatt Arsenault2016-12-142-0/+19
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-121-5/+4
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-102-14/+71
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