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path: root/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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* [AMDGPU] Revert scheduling to reduce spillingStanislav Mekhanoshin2020-01-031-2/+11
* [AMDGPU] Add VerifyScheduling support.Jay Foad2019-10-011-0/+18
* Add tracing in pickNodeFromQueue.Jay Foad2019-09-251-0/+1
* AMDGPU: Fix typoMatt Arsenault2019-09-061-4/+4
* AMDGPU: Avoid constructing new std::vector in initCandidateMatt Arsenault2019-09-051-2/+2
* [AMDGPU] Speed up live-in virtual register set computaion in GCNScheduleDAGMI...Valery Pykhtin2019-06-181-2/+26
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Refactor Subtarget classesTom Stellard2018-07-111-2/+2
* [AMDGPU] Small refactoring in the schedulerStanislav Mekhanoshin2018-06-041-18/+3
* [AMDGPU] Track occupancy in MFIStanislav Mekhanoshin2018-05-311-7/+4
* [AMDGPU] Add perf hints to functionsStanislav Mekhanoshin2018-05-251-1/+11
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-40/+37
* [AMDGPU] Fix amdgpu-waves-per-eu accounting in schedulerStanislav Mekhanoshin2018-05-121-2/+5
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-3/+3
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-221-1/+1
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
* Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-151-8/+11
* Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-141-11/+8
* CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu2017-12-131-8/+11
* AMDGPU: Fix crash when scheduling DBG_VALUEMatt Arsenault2017-12-051-1/+5
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-3/+2
* [CodeGen] Rename DEBUG_TYPE to match passnamesEvandro Menezes2017-07-111-1/+1
* [AMDGPU] Use GCNRPTracker dumper methods in schedulerStanislav Mekhanoshin2017-05-161-18/+7
* [AMDGPU] Cache live-ins and register pressure in schedulerStanislav Mekhanoshin2017-05-161-71/+140
* [AMDGPU] Turn register pressure estimation into forward trackerStanislav Mekhanoshin2017-05-161-112/+39
* [AMDGPU] Fix incorrect register pressure calculationStanislav Mekhanoshin2017-05-111-2/+3
* AMDGPU: Fix assert in schedulerKonstantin Zhuravlyov2017-04-271-1/+2
* [AMDGPU] Fix recorded region boundaries in max-occupancy schedulerStanislav Mekhanoshin2017-03-281-10/+5
* [AMDGPU] Iterative scheduling infrastructure + minimal registry schedulerValery Pykhtin2017-03-211-3/+1
* [AMDGPU] Remove getBidirectionalReasonRankStanislav Mekhanoshin2017-03-111-13/+1
* [AMDGPU] Add second pass of the schedulerStanislav Mekhanoshin2017-02-281-5/+97
* [AMDGPU] New method to estimate register pressureStanislav Mekhanoshin2017-02-281-21/+135
* [AMDGPU] Fix read-undef flags when schedule is revertedStanislav Mekhanoshin2017-02-281-12/+15
* [AMDGPU] Revert failed schedulingStanislav Mekhanoshin2017-02-151-29/+88
* [AMDGPU] Move register related queries to subtarget classKonstantin Zhuravlyov2017-02-081-2/+2
* [AMDGPU] Fix GCNSchedStrategy.cpp debug outputStanislav Mekhanoshin2017-02-061-2/+2
* [AMDGPU] Account workgroup size in LDS occupancy limitsStanislav Mekhanoshin2017-02-011-1/+2
* [AMDGPU] Fix typo in GCNSchedStrategyValery Pykhtin2017-01-261-1/+1
* AMDGPU/SI: Allow using SGPRs 96-101 on VIMarek Olsak2016-12-091-1/+1
* AMDGPU: Whitespace fixesMatt Arsenault2016-11-011-2/+2
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-2/+2
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-0/+312
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