diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-05-11 17:16:55 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-05-11 17:16:55 +0000 |
| commit | 33a97ec4ed4e5a2e49823ce1a690e26ace7b72da (patch) | |
| tree | cda1cce4221ce67795639c76ec7d4abe7623134f /llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | |
| parent | 0aca09fc6cdcda65a44dc084b20d7056912977ef (diff) | |
| download | bcm5719-llvm-33a97ec4ed4e5a2e49823ce1a690e26ace7b72da.tar.gz bcm5719-llvm-33a97ec4ed4e5a2e49823ce1a690e26ace7b72da.zip | |
[AMDGPU] Fix incorrect register pressure calculation
Earlier fix D32572 introduced a bug where live-ins were calculated
for basic block instead of scheduling region. This change fixes it.
Differential Revision: https://reviews.llvm.org/D33086
llvm-svn: 302812
Diffstat (limited to 'llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 630442625aa..9f07d28c708 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -422,9 +422,10 @@ void GCNScheduleDAGMILive::discoverLiveIns() { unsigned SGPRs = 0; unsigned VGPRs = 0; - auto &MI = *begin()->getParent()->getFirstNonDebugInstr(); + auto I = begin(); + I = skipDebugInstructionsForward(I, I->getParent()->end()); const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); - SlotIndex SI = LIS->getInstructionIndex(MI).getBaseIndex(); + SlotIndex SI = LIS->getInstructionIndex(*I).getBaseIndex(); assert (SI.isValid()); DEBUG(dbgs() << "Region live-ins:"); |
