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path: root/llvm/lib/Target/AMDGPU/BUFInstructions.td
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* AMDGPU: Eliminate more legacy codepred address space PatFragsMatt Arsenault2020-01-091-2/+2
* [AMDGPU] drop getIsFP td helperStanislav Mekhanoshin2019-10-171-2/+2
* [AMDGPU][MC][GFX6][GFX7][GFX10] Added instructions buffer_atomic_[fcmpswap/fm...Dmitry Preobrazhensky2019-10-111-14/+29
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-119/+177
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-55/+55
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-55/+55
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-55/+55
* AMDGPU/GlobalISel: Avoid repeating 32-bit type listsMatt Arsenault2019-09-061-2/+2
* AMDGPU/GlobalISel: Fix load/store of types in other address spacesMatt Arsenault2019-09-061-1/+8
* AMDGPU: Disambiguate v3f16 format in load/store tablesMatt Arsenault2019-08-181-95/+105
* AMDGPU: Correct behavior of f16 buffer loadsMatt Arsenault2019-08-051-0/+4
* AMDGPU: Correct behavior of f16/i16 non-format store intrinsicsMatt Arsenault2019-08-051-0/+4
* AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}Nicolai Haehnle2019-08-051-0/+4
* AMDGPU: Start redefining atomic PatFragsMatt Arsenault2019-08-011-24/+24
* AMDGPU: Correct FP atomic patternsMatt Arsenault2019-08-011-2/+2
* AMDGPU/GlobalISel: Fix selection of private storesMatt Arsenault2019-07-161-6/+7
* AMDGPU: Redefine load PatFragsMatt Arsenault2019-07-161-2/+2
* AMDGPU: Avoid code predicates for extload PatFragsMatt Arsenault2019-07-161-9/+18
* AMDGPU: Use standalone MUBUF load patternsMatt Arsenault2019-07-151-20/+37
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-0/+58
* AMDGPU: Remove mubuf specific PatFragsMatt Arsenault2019-07-081-27/+13
* [AMDGPU] hazard recognizer for fp atomic to s_denorm_modeStanislav Mekhanoshin2019-06-211-2/+21
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-202/+383
* [AMDGPU] Sort out and rename multiple CI/VI predicatesStanislav Mekhanoshin2019-04-061-8/+8
* [AMDGPU] predicate and feature refactoringStanislav Mekhanoshin2019-04-051-15/+16
* [AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsicsTim Renouf2019-03-221-4/+14
* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-5/+4
* [AMDGPU] Add buffer/load 8/16 bit overloaded intrinsicsRyan Taylor2019-03-191-0/+6
* AMDGPU: Move d16 load matching to preprocess stepMatt Arsenault2019-03-081-56/+19
* [AMDGPU] Add support for 64 bit buffer atomic artihmetic instructionsRyan Taylor2019-03-061-20/+30
* Revert "AMDGPU/NFC: Cleanup subtarget predicates"Konstantin Zhuravlyov2019-02-221-13/+13
* AMDGPU/NFC: Cleanup subtarget predicatesKonstantin Zhuravlyov2019-02-211-13/+13
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AMDGPU] Extend the SI Load/Store optimizer to combine more things.Neil Henning2018-12-121-0/+41
* AMDGPU: Remove llvm.SI.buffer.load.dwordMatt Arsenault2018-12-071-48/+0
* AMDGPU/NFC: Split MUBUF_Pseudo_Atomics into RTN/NO_RTN multiclassesKonstantin Zhuravlyov2018-11-071-5/+16
* AMDGPU: Remove dead TableGen codeNicolai Haehnle2018-10-171-2/+0
* AMDGPU: Remove remnants of old address space mappingMatt Arsenault2018-08-311-2/+2
* [AMDGPU] Allow int types for MUBUF vdataTim Renouf2018-08-211-0/+20
* [AMDGPU] New buffer intrinsicsTim Renouf2018-08-211-62/+52
* [AMDGPU] New tbuffer intrinsicsTim Renouf2018-08-211-49/+57
* AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle2018-06-211-4/+4
* AMDGPU: Make v4i16/v4f16 legalMatt Arsenault2018-06-151-8/+4
* [AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4Dmitry Preobrazhensky2018-06-131-3/+19
* AMDGPU: Make various NamedOperands upper caseNicolai Haehnle2018-06-041-14/+14
* TableGen: Streamline the semantics of NAMENicolai Haehnle2018-06-041-36/+36
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-6/+6
* AMDGPU: Add D16 instructions preserve unused bits featureKonstantin Zhuravlyov2018-05-041-2/+2
* [AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CIDmitry Preobrazhensky2018-04-041-1/+1
* [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_xDmitry Preobrazhensky2018-03-281-0/+10
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