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path: root/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
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* AMDGPU: Change stack alignmentMatt Arsenault2017-04-171-2/+4
* [AMDGPU] Generate range metadata for workitem idStanislav Mekhanoshin2017-04-121-0/+3
* [AMDGPU] Get address space mapping by target triple environmentYaxun Liu2017-03-271-0/+5
* AMDGPU: Always use VGPR indexing on GFX9Marek Olsak2017-03-211-0/+4
* [AMDGPU] Iterative scheduling infrastructure + minimal registry schedulerValery Pykhtin2017-03-211-0/+6
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-0/+4
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-271-0/+5
* AMDGPU : Update TrapCode based on Trap Handler ABI.Wei Ding2017-02-221-6/+10
* Revert "AMDGPU : Update TrapCode based on Trap Handler ABI."Wei Ding2017-02-221-10/+6
* AMDGPU : Update TrapCode based on Trap Handler ABI.Wei Ding2017-02-221-6/+10
* AMDGPU: Redefine clamp node as clamp 0.0-1.0Matt Arsenault2017-02-211-4/+9
* AMDGPU: Fix assembler subtarget predicate for gfx9Matt Arsenault2017-02-181-0/+1
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-1/+23
* AMDGPU : Add trap handler support.Wei Ding2017-02-101-0/+25
* [AMDGPU] Add target information that is required by tools to metadataKonstantin Zhuravlyov2017-02-081-50/+43
* [AMDGPU] Distinguish between S/VGPR allocation and encoding granularitiesKonstantin Zhuravlyov2017-02-081-0/+12
* [AMDGPU] Move register related queries to subtarget classKonstantin Zhuravlyov2017-02-081-1/+79
* [AMDGPU] Account workgroup size in LDS occupancy limitsStanislav Mekhanoshin2017-02-011-2/+3
* AMDGPU: Cleanup fmin/fmax legacy functionMatt Arsenault2017-02-011-0/+4
* AMDGPU: Implement hook for InferAddressSpacesMatt Arsenault2017-01-311-4/+4
* Re-commit AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+15
* Revert "AMDGPU/GlobalISel: Add support for simple shaders"Tom Stellard2017-01-301-15/+0
* AMDGPU/GlobalISel: Add support for simple shadersTom Stellard2017-01-301-0/+15
* AMDGPU: Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-271-1/+0
* AMDGPU: Implement early ifcvt target hooks.Matt Arsenault2017-01-251-0/+5
* AMDGPU add support for spilling to a user sgpr pointed buffersTom Stellard2017-01-251-7/+16
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-0/+1
* AMDGPU: Combine fp16/fp64 subtarget featuresMatt Arsenault2017-01-231-4/+3
* [AMDGPU] Add subtarget features for SDWA/DPPSam Kolton2017-01-201-0/+10
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-091-5/+12
* [AMDGPU] Scalarization of global uniform loads.Alexander Timofeev2016-12-081-0/+4
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-0/+4
* [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32Konstantin Zhuravlyov2016-11-011-4/+4
* AMDGPU: Use 1/2pi inline imm on VIMatt Arsenault2016-10-291-0/+5
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-0/+5
* AMDGPU: Diagnose using too many SGPRsMatt Arsenault2016-10-281-0/+2
* AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard2016-10-271-0/+4
* AMDGPU: Refactor processor definition to use ISA version featuresYaxun Liu2016-10-261-1/+4
* AMDGPU : Add a function to enable and disable IEEEBit for SC and shaderWei Ding2016-10-191-0/+4
* AMDGPU/SI: Don't allow unaligned scratch accessTom Stellard2016-10-141-0/+5
* AMDGPU: Add instruction definitions for VGPR indexingMatt Arsenault2016-10-121-0/+10
* AMDGPU/SI: Update ISA version numbers for Tonga and Polaris10/11.Changpeng Fang2016-10-111-0/+1
* [AMDGPU] Ask subtarget if waitcnt instruction is needed before barrier instru...Konstantin Zhuravlyov2016-09-301-0/+6
* AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_sizeTom Stellard2016-09-231-0/+14
* AMDGPU: Use i64 scalar compare instructionsMatt Arsenault2016-09-171-0/+4
* AMDGPU/SI: Add support for triples with the mesa3d operating systemTom Stellard2016-09-161-1/+9
* AMDGPU/SI: Make sure llvm.amdgcn.implicitarg.ptr() is 8-byte aligned for HSATom Stellard2016-09-091-0/+4
* [AMDGPU] Wave and register controlsKonstantin Zhuravlyov2016-09-061-8/+83
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-0/+6
* AMDGPU: Fix crashes on memory functionsMatt Arsenault2016-08-111-0/+7
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