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path: root/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
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* AMDGPU/GlobalISel: Select mul24 intrinsicsMatt Arsenault2019-12-301-2/+10
* AMDGPU/GlobalISel: Select llvm.amdgcn.fmad.ftzMatt Arsenault2019-12-301-1/+5
* AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn.div.fixupMatt Arsenault2019-12-241-1/+5
* AMDGPU: Select basic interp directly from intrinsicsMatt Arsenault2019-10-211-12/+0
* AMDGPU/GlobalISel: Select cvt pk intrinsicsMatt Arsenault2019-09-101-5/+25
* AMDGPU/GlobalISel: Select llvm.amdgcn.sffbhMatt Arsenault2019-09-101-1/+5
* AMDGPU/GlobalISel: Select llvm.amdgcn.classMatt Arsenault2019-09-091-1/+5
* AMDGPU/GlobalISel: Select fmed3Matt Arsenault2019-09-091-1/+5
* AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsicsMatt Arsenault2019-09-091-10/+39
* AMDGPU: Remove pointless wrapper nodes for init.exec intrinsicsMatt Arsenault2019-09-091-9/+0
* AMDGPU: Remove unused custom node definitionMatt Arsenault2019-09-011-8/+0
* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-201-4/+4
* [AMDGPU] gfx1010 AMDGPUSetCCOp definitionStanislav Mekhanoshin2019-06-131-1/+1
* [AMDGPU] gfx1010 allows VOP3 to have a literalStanislav Mekhanoshin2019-05-021-11/+2
* [AMDGPU] Support emitting GOT relocations for function callsScott Linder2019-02-041-3/+2
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-281-0/+11
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle2018-10-311-8/+0
* AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov2018-08-011-2/+3
* [AMDGPU] [AMDGPU] Support a fdot2 pattern.Farhana Aleen2018-07-161-0/+5
* [AMDGPU] Convert rcp to rcp_iflagStanislav Mekhanoshin2018-06-271-0/+2
* [AMDGPU] DAG combine to produce V_PERM_B32Stanislav Mekhanoshin2018-06-121-0/+2
* AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard2018-05-241-2/+0
* AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}Marek Olsak2018-01-311-0/+8
* Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.Wei Ding2017-10-121-0/+2
* AMDGPU: Start adding tail call supportMatt Arsenault2017-08-111-0/+6
* AMDGPU: Initial implementation of callsMatt Arsenault2017-08-011-0/+16
* [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin2017-06-211-0/+10
* AMDGPU: Start defining a calling conventionMatt Arsenault2017-05-171-1/+1
* AMDGPU: Add new amdgcn.init.exec intrinsicsMarek Olsak2017-04-281-0/+9
* AMDGPU: Move trap lowering to DAGMatt Arsenault2017-04-241-0/+5
* AMDGPU: Remove unnecessary ands when f16 is legalMatt Arsenault2017-03-311-0/+1
* AMDGPU: Rename SI_RETURNMatt Arsenault2017-03-211-1/+5
* AMDGPU: Cleanup control flow intrinsicsMatt Arsenault2017-03-171-0/+28
* AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault2017-03-151-0/+2
* AMDGPU : Replace FMAD with FMA when denormals are enabled.Wei Ding2017-02-241-0/+2
* AMDGPU: Add cvt.pkrtz intrinsicMatt Arsenault2017-02-221-0/+6
* AMDGPU: Redefine clamp node as clamp 0.0-1.0Matt Arsenault2017-02-211-1/+1
* AMDGPU: Remove dead node definitionsMatt Arsenault2017-02-151-10/+0
* AMDGPU/R600: Serialize vector trunc stores to private ASJan Vesely2017-01-201-0/+3
* AMDGPU: Add replacement export intrinsicsMatt Arsenault2017-01-171-8/+9
* AMDGPU/SI: Implement sendmsghalt intrinsicJan Vesely2017-01-041-0/+4
* AMDGPU : Add S_SETREG instructions to fix fdiv precision issues.Tom Stellard2016-12-071-0/+13
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-051-0/+26
* AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault2016-08-271-4/+11
* AMDGPU : Add intrinsics for compare with the full wavefront resultWei Ding2016-07-281-0/+5
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-261-0/+5
* AMDGPU: Only use legal inline immediates with kill pseudoMatt Arsenault2016-07-191-0/+5
* AMDGPU: Add intrinsic for s_flbit_i32/v_ffbh_i32Matt Arsenault2016-07-181-0/+1
* AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault2016-06-221-1/+4
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