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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-11 20:42:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-08-11 20:42:08 +0000 |
| commit | 71bcbd451ff7460f12c77b97ecdc29c7dbd19bf0 (patch) | |
| tree | 273dabb06f4e6d1ad833082b00f4703dde8b94b3 /llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | |
| parent | 964e096345084b4ea1edba30c82f6f38d9c0884a (diff) | |
| download | bcm5719-llvm-71bcbd451ff7460f12c77b97ecdc29c7dbd19bf0.tar.gz bcm5719-llvm-71bcbd451ff7460f12c77b97ecdc29c7dbd19bf0.zip | |
AMDGPU: Start adding tail call support
Handle the sibling call cases.
llvm-svn: 310753
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index 196e699870e..d8b03c6aab4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -74,6 +74,8 @@ def AMDGPUAddeSubeOp : SDTypeProfile<2, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisVT<0, i32>, SDTCisVT<1, i1>, SDTCisVT<4, i1>] >; +def SDT_AMDGPUTCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; + //===----------------------------------------------------------------------===// // AMDGPU DAG Nodes // @@ -98,6 +100,10 @@ def AMDGPUcall : SDNode<"AMDGPUISD::CALL", SDNPVariadic] >; +def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN", SDT_AMDGPUTCRET, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic] +>; + def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP", SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>, [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue] |
