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* [AArch64] Skip debug ops with regsOverlap in AArch64 LD/ST opt.Florian Hahn2019-12-111-1/+1
* Revert "[AArch64][SVE] Implement intrinsics for non-temporal loads & stores"Kerry McLaughlin2019-12-113-98/+2
* [AArch64] Teach Load/Store optimizier to rename store operands for pairing.Florian Hahn2019-12-111-8/+322
* [AArch64][SVE] Add DAG combine rules for gather loads and sext/zextAndrzej Warzynski2019-12-113-48/+204
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Oliver Stannard2019-12-111-288/+8
* [AArch64][SVE] Implement intrinsics for non-temporal loads & storesKerry McLaughlin2019-12-113-2/+98
* [AArch64] Fix issues with large arrays on stackKiran Chandramohan2019-12-105-27/+26
* [AArch64][SVE] Add wide compare immediate patternsCullen Rhodes2019-12-101-0/+101
* [AArch64][SVE] Implement SPLAT_VECTOR for i1 vectors.Eli Friedman2019-12-091-13/+18
* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-092-2/+4
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-092-11/+69
* Revert "[DebugInfo] Make describeLoadedValue() reg aware"David Stenberg2019-12-092-69/+11
* [DebugInfo] Make describeLoadedValue() reg awareDavid Stenberg2019-12-092-11/+69
* [AArch64][GlobalISel] Add missing default statement to a switch in the selector.Amara Emerson2019-12-061-0/+3
* Move variable only used in an assert into the assert itself.Sterling Augustine2019-12-061-2/+1
* [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.Amara Emerson2019-12-061-5/+71
* [AArch64] Fix a bug with jump table generationCullen Rhodes2019-12-062-4/+27
* [AArch64][SVE2] Implement while comparison intrinsicsCullen Rhodes2019-12-061-10/+9
* [AArch64][SVE] Implement integer compare intrinsicsCullen Rhodes2019-12-063-34/+168
* [AArch64] Fix MUL/SUB fusingSanne Wouda2019-12-051-20/+90
* [AArch64][SVE] Integer reduction instructions pattern/intrinsics.Danilo Carvalho Grael2019-12-055-14/+106
* [AArch64][SVE] Implement element count intrinsicsCullen Rhodes2019-12-052-7/+16
* [AArch64][SVE] Add intrinsics and patterns for logical predicate instructionsDanilo Carvalho Grael2019-12-042-17/+27
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-051-8/+288
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Sterling Augustine2019-12-041-284/+8
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-041-8/+284
* [SVE][AArch64] Adding patterns for while intrinsics.Mikhail Gudim2019-12-042-28/+40
* [AArch64][SVE] Implement reversal intrinsicsCullen Rhodes2019-12-042-8/+37
* [AArch64TTI] Compute imm materialization cost for AArch64 intrinsicsFlorian Hahn2019-12-041-0/+6
* [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADDSanne Wouda2019-12-032-8/+362
* [Aarch64][SVE] Add intrinsics for gather loads (vector + imm)Sander de Smalen2019-12-034-29/+47
* [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsetsSander de Smalen2019-12-034-46/+98
* [AArch64][SVE2] Implement remaining SVE2 floating-point intrinsicsKerry McLaughlin2019-12-032-17/+42
* [AArch64][SVE] Add intrinsics for gather loads with 64-bit offsetsSander de Smalen2019-12-036-29/+158
* [AArch64][SVE] Implement shift intrinsicsKerry McLaughlin2019-12-035-21/+69
* [MIBundles] Move analyzePhysReg out of MIBundleOperands iterator (NFC).Florian Hahn2019-12-021-2/+1
* [ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-AVictor Campos2019-12-021-0/+23
* Revert 651f07908a1 "[AArch64] Don't combine callee-save and local stack adjus...Hans Wennborg2019-11-301-3/+0
* [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.Simon Tatham2019-11-281-1/+1
* AArch64: support the Apple NEON syntax for v8.2 crypto instructions.Tim Northover2019-11-271-11/+15
* [Codegen][ARM] Add addressing modes from masked loads and storesDavid Green2019-11-261-11/+16
* [AArch64][SVE] Implement floating-point conversion intrinsicsKerry McLaughlin2019-11-262-41/+64
* [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOpDavid Tellenbach2019-11-231-1/+1
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-222-1/+1014
* [AArch64] [FrameLowering] Allow conditional insertion of CFI instructionDavid Tellenbach2019-11-221-7/+7
* [PGO][PGSO] DAG.shouldOptForSize part.Hiroshi Yamauchi2019-11-212-9/+5
* [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"Tom Stellard2019-11-215-5/+5
* Revert "[AArch64] Add the pipeline model for Exynos M5"Eric Christopher2019-11-202-1014/+1
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-202-1/+1014
* ExecutionEngine: add preliminary support for COFF ARM64Adam Kallai2019-11-201-1/+4
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