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path: root/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+2
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-261-0/+10
* [AArch64] Attempt to parse more operands as expressionsDavid Green2018-09-181-24/+11
* [AArch64] Add Tiny Code Model for AArch64David Green2018-08-221-8/+25
* [AArch64] Disallow the MachO specific .loh directive for windowsMartin Storsjo2018-08-011-6/+6
* [AArch64] Support the .inst directive for MachO and COFF targetsMartin Storsjo2018-07-311-6/+5
* [AArch64][SVE] Asm: Add MOVPRFX instructions.Sander de Smalen2018-07-301-4/+144
* [AArch64] Armv8.2-A: add the crypto extensionsSjoerd Meijer2018-07-261-1/+57
* [AArch64][SVE] Asm: Support for ADR instruction.Sander de Smalen2018-07-091-6/+21
* Recommit: [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-0/+16
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-4/+15
* Try to fix -Wimplicit-fallthrough warning. NFCI.Simon Pilgrim2018-07-051-0/+1
* [AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABDSander de Smalen2018-07-051-0/+3
* [AArch64][SVE] Asm: Support for SVE condition code aliasesSander de Smalen2018-07-041-0/+16
* [AArch64][SVE] Asm: Support for FP Complex ADD/MLA.Sander de Smalen2018-07-031-4/+6
* [AArch64][SVE] Asm: Support for FMUL (indexed)Sander de Smalen2018-07-031-0/+20
* [AArch64] Armv8.4-A: system registersSjoerd Meijer2018-07-031-0/+1
* [AArch64][SVE] Asm: Support for vector element FP compare.Sander de Smalen2018-07-031-1/+1
* Reapply r334980 and r334983.Sander de Smalen2018-07-021-18/+94
* Revert r334980 and 334983Vlad Tsyrklevich2018-06-201-94/+18
* [AArch64][SVE] Asm: Fix predicate pattern diagnostics.Sander de Smalen2018-06-181-4/+6
* [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions.Sander de Smalen2018-06-181-14/+88
* [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.Sander de Smalen2018-06-151-12/+31
* [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.Sander de Smalen2018-06-151-0/+9
* [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.Sander de Smalen2018-06-151-45/+100
* [AArch64][SVE] Fix range for DUP immediates (16bit elts)Sander de Smalen2018-06-041-0/+2
* [AArch64][SVE] Asm: Print indexed element 0 as FPR.Sander de Smalen2018-06-041-0/+20
* [AArch64][SVE] Asm: Support for indexed DUP instructions.Sander de Smalen2018-06-041-28/+35
* [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.Sander de Smalen2018-06-011-0/+6
* [AArch64][AsmParser] Fix segfault on illegal fpimm.Sander de Smalen2018-05-301-2/+2
* [AArch64][SVE] Asm: Support for ADD (immediate) instructions.Sander de Smalen2018-05-291-14/+35
* Fix ubsan errors introduced by r333263 re. left-shifting negative values.Sander de Smalen2018-05-251-2/+3
* [AArch64][SVE] Asm: Support for DUP (immediate) instructions.Sander de Smalen2018-05-251-27/+81
* [AArch64] Use addAliasForDirective to support data directivesAlex Bradbury2018-05-231-23/+7
* [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.Sander de Smalen2018-05-161-8/+38
* [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.Sander de Smalen2018-05-161-2/+5
* [AArch64][SVE] Extend parsing of Prefetch operation for SVE.Sander de Smalen2018-05-141-6/+29
* [AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.Sander de Smalen2018-05-081-0/+12
* [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector ins...Sander de Smalen2018-05-021-0/+3
* [AArch64][SVE] Asm: Improve diagnostics for gather loads.Sander de Smalen2018-04-301-4/+15
* [AArch64][AsmParser] NFC: Cleanup of addOperands functionsSander de Smalen2018-04-291-144/+3
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instruct...Sander de Smalen2018-04-291-4/+27
* [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.Sander de Smalen2018-04-261-14/+27
* [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing ...Sander de Smalen2018-04-251-4/+84
* [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:Sander de Smalen2018-04-201-1/+1
* [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.Sander de Smalen2018-04-201-0/+24
* [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.Sander de Smalen2018-04-201-36/+112
* [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.Sander de Smalen2018-04-191-77/+69
* [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.Sander de Smalen2018-04-161-3/+6
* [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.Sander de Smalen2018-04-161-3/+7
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