| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to... | Abderrazek Zaafrani | 2017-12-08 | 1 | -735/+0 |
| * | [AArch64] Avoid SIMD interleaved store instruction for Exynos. | Abderrazek Zaafrani | 2017-12-08 | 1 | -118/+465 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -1/+1 |
| * | Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering | David Blaikie | 2017-11-08 | 1 | -1/+1 |
| * | [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; ot... | Eugene Zelenko | 2017-01-25 | 1 | -4/+21 |
| * | [AArch64] Avoid generating indexed vector instructions for Exynos | Sebastian Pop | 2016-10-08 | 1 | -0/+371 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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