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path: root/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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* Sink some IntrinsicInst.h and Intrinsics.h out of llvm/includeReid Kleckner2017-09-071-0/+1
* [AArch64][Falkor] Attempt to fix Windows buildbotsGeoff Berry2017-06-281-1/+1
* [AArch64][Falkor] Try to avoid exhausting HW prefetcher resources when unroll...Geoff Berry2017-06-281-0/+59
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-281-2/+2
* [AArch64] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-06-271-0/+14
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* Re-commit r302678, fixing PR33053.Amara Emerson2017-05-161-0/+25
* Revert r302678 "[AArch64] Enable use of reduction intrinsics."Hans Wennborg2017-05-151-23/+0
* [AArch64] Enable use of reduction intrinsics.Amara Emerson2017-05-101-0/+23
* [AArch64] Consider widening instructions in cost calculationsMatthew Simpson2017-05-091-6/+100
* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-121-4/+6
* [ARM/AArch64] Ensure valid vector element types for interleaved accessesMatthew Simpson2017-04-101-4/+4
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-031-0/+32
* TTI: Split IsSimple in MemIntrinsicInfoMatt Arsenault2017-03-241-4/+0
* [ARM/AArch64] Update costs for interleaved accesses with wide typesMatthew Simpson2017-03-021-2/+4
* [X86] updating TTI costs for arithmetic instructions on X86\SLM arch.Mohammed Agabaria2017-01-111-1/+1
* [AArch64] Consider all vector types for FeatureSlowMisaligned128StoreEvandro Menezes2017-01-101-12/+11
* Currently isLikelyComplexAddressComputation tries to figure out if the given ...Mohammed Agabaria2017-01-051-2/+5
* [AArch64] Guard Misaligned 128-bit store penalty by subtarget featureMatthew Simpson2016-12-151-1/+2
* AArch64: Do not test for CPUs, use SubtargetFeaturesMatthias Braun2016-06-021-21/+6
* Add parentheses to silence buildbot warningMatthew Simpson2016-04-271-2/+2
* [TTI] Add hook for vector extract with extensionMatthew Simpson2016-04-271-0/+55
* [LoopDataPrefetch] Centralize the tuning cl::opts under the passAdam Nemet2016-03-291-21/+6
* [LoopDataPrefetch] Add TTI to limit the number of iterations to prefetch aheadAdam Nemet2016-03-181-0/+13
* [LoopDataPrefetch/Aarch64] Allow selective prefetching of large-strided accessesAdam Nemet2016-03-181-0/+12
* [Aarch64] Add pass LoopDataPrefetch for CycloneAdam Nemet2016-03-181-0/+17
* [AArch64] Reduce vector insert/extract cost for KryoMatthew Simpson2016-02-181-0/+2
* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-121-1/+1
* [AArch64][ARM] Don't base interleaved op legality on type alloc size.Ahmed Bougacha2015-12-091-1/+1
* [EarlyCSE] IsSimple vs IsVolatile naming clarification (NFC)Philip Reames2015-12-051-2/+2
* [Aarch64] Add cost for missing extensions.Matthew Simpson2015-11-181-17/+18
* Remove templates from CostTableLookup functions. All instantiations had the s...Craig Topper2015-10-281-2/+2
* Convert cost table lookup functions to return a pointer to the entry or nullp...Craig Topper2015-10-271-9/+8
* Use MVT::SimpleValueType instead of MVT in template parameter. NFCCraig Topper2015-10-251-1/+2
* Call the version of ConvertCostTableLookup that takes a statically sized arra...Craig Topper2015-10-241-3/+2
* [CostModel][AArch64] Remove amortization factor for some of the vector select...Silviu Baranga2015-09-091-4/+5
* [CostModel][AArch64] Increase cost of vector insert element and add missing c...Silviu Baranga2015-08-171-1/+33
* [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'Chandler Carruth2015-08-051-39/+38
* [ARM/AArch64] Fix cost model for interleaved accessesSilviu Baranga2015-07-271-1/+1
* Remove getDataLayout() from TargetLoweringMehdi Amini2015-07-091-1/+1
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-7/+7
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch...Hao Liu2015-06-261-0/+20
* [AArch64] Revert r239711 again. We need to discuss how to share code between ...Hao Liu2015-06-151-12/+0
* [AArch64] Match interleaved memory accesses into ldN/stN instructions.Hao Liu2015-06-151-0/+12
* This reverts commit r239529 and r239514.Rafael Espindola2015-06-111-12/+0
* [AArch64] Match interleaved memory accesses into ldN/stN instructions.Hao Liu2015-06-111-0/+12
* [X86] Disable loop unrolling in loop vectorization pass when VF is 1.Wei Mi2015-05-061-1/+1
* [AArch64] Enable partial & runtime unrolling on cortex-a57Kevin Qin2015-03-091-0/+10
* Make some non-constant static variables non-static or fully const.Benjamin Kramer2015-03-011-1/+1
* [multiversion] Remove the function parameter from the unrollingChandler Carruth2015-02-011-1/+1
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