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* [globalisel][tablegen] Generate rule coverage and use it to identify untested...Daniel Sanders2017-11-161-4/+5
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-151-3/+3
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-4/+14
* [AArch64] Refactor the loads and stores optimizerEvandro Menezes2017-11-151-143/+143
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-17/+14
* [AArch64][SVE] Asm: Report SVE parsing diagnostics only onceSander de Smalen2017-11-151-25/+36
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-141-11/+9
* [ARM, AArch64] Fix an assert message, Darwin isn't the only target supporting...Martin Storsjo2017-11-141-1/+2
* Test commitSander de Smalen2017-11-131-1/+1
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-0812-12/+12
* [AArch64][SVE] Asm: Add support for (ADD|SUB)_ZZZFlorian Hahn2017-11-073-0/+60
* [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing supportFlorian Hahn2017-11-075-1/+330
* [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler mod...Florian Hahn2017-11-078-0/+16
* [AArch64][SVE] Asm: Replace 'IsVector' by 'RegKind' in AArch64AsmParser (NFC)Florian Hahn2017-11-072-46/+69
* [GlobalISel] Enable legalizing non-power-of-2 sized types.Kristof Beyls2017-11-071-41/+128
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-032-2/+2
* [AArch64] Fix the number of iterations for the Newton seriesEvandro Menezes2017-11-031-1/+1
* [AArch64] Use dwarf exception handling on MinGWMartin Storsjo2017-11-032-1/+11
* [AArch64][RegisterBankInfo] Add mapping for G_FPEXT.Quentin Colombet2017-11-023-1/+89
* [AArch64][RegisterBankInfo] Add FPR16 support in value mapping.Quentin Colombet2017-11-023-35/+48
* [AArch64]: range loopify frame-loweringJaved Absar2017-10-301-2/+2
* [SimplifyCFG] use pass options and remove the latesimplifycfg passSanjay Patel2017-10-281-1/+1
* InstructionSelectorImpl.h: Modularize/remove ODR violations by using a static...David Blaikie2017-10-261-2/+2
* Clear LastMappingSymbols and LastEMS(Info) when resetting the ARM(AArch64)ELF...Yichao Yu2017-10-261-0/+8
* [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ...Craig Topper2017-10-261-1/+2
* [AsmParser][TableGen] Make the generated mnemonic spell checker function a fi...Craig Topper2017-10-261-1/+2
* [AArch64] Add support for dllimport of values and functionsMartin Storsjo2017-10-254-20/+63
* [globalisel][tablegen] Import stores and allow GISel to automatically substit...Daniel Sanders2017-10-233-8/+34
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-14/+14
* [aarch64][globalisel] Register banks and classes should have distinct names.Daniel Sanders2017-10-182-5/+4
* AArch64: Enable AES instruction fusion on Cyclone.Matthias Braun2017-10-171-2/+5
* AArch64: account for possible frame index operand in compares.Tim Northover2017-10-172-0/+9
* Re-apply [AArch64][RegisterBankInfo] Use the statically computed mappings for...Quentin Colombet2017-10-161-4/+35
* [AArch64][RegisterBankInfo] Add mapping support for G_BITCAST of s128Quentin Colombet2017-10-161-2/+2
* [AArch64][LegalizerInfo] Mark s128 G_BITCAST legalQuentin Colombet2017-10-161-1/+3
* [aarch64][globalisel] Fix a crash in selectAddrModeIndexed() caused by incorr...Daniel Sanders2017-10-161-1/+5
* Re-commit r315885: [globalisel][tblgen] Add support for iPTR and implement am...Daniel Sanders2017-10-162-0/+158
* Revert r315885: [globalisel][tblgen] Add support for iPTR and implement am_un...Daniel Sanders2017-10-162-158/+0
* [globalisel][tblgen] Add support for iPTR and implement am_unscaled* and am_i...Daniel Sanders2017-10-162-0/+158
* Re-commit r315863: [globalisel][tablegen] Import ComplexPattern when used as ...Daniel Sanders2017-10-151-5/+8
* Revert r315863: [globalisel][tablegen] Import ComplexPattern when used as an ...Daniel Sanders2017-10-151-8/+5
* [globalisel][tablegen] Import ComplexPattern when used as an operatorDaniel Sanders2017-10-151-5/+8
* Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for ...Bruno Cardoso Lopes2017-10-141-32/+4
* [AArch64][RegisterBankInfo] Use the statically computed mappings for COPYQuentin Colombet2017-10-141-4/+32
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat base...Daniel Sanders2017-10-131-0/+5
* [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 us...Daniel Sanders2017-10-131-16/+15
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-4/+5
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-122-5/+4
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-115-31/+41
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+1
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