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author | Matthew Simpson <mssimpso@codeaurora.org> | 2017-04-10 18:34:37 +0000 |
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committer | Matthew Simpson <mssimpso@codeaurora.org> | 2017-04-10 18:34:37 +0000 |
commit | 1468d3e04ee4f93e7951e902afbc74e585243f3f (patch) | |
tree | b284aae10829b331611f33dd37f565ab2936b716 /llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | |
parent | 0d830ff7bf86e68d53931259af81dfa70bb9935b (diff) | |
download | bcm5719-llvm-1468d3e04ee4f93e7951e902afbc74e585243f3f.tar.gz bcm5719-llvm-1468d3e04ee4f93e7951e902afbc74e585243f3f.zip |
[ARM/AArch64] Ensure valid vector element types for interleaved accesses
This patch refactors and strengthens the type checks performed for interleaved
accesses. The primary functional change is to ensure that the interleaved
accesses have valid element types. The added test cases previously failed
because the element type is f128.
Differential Revision: https://reviews.llvm.org/D31817
llvm-svn: 299864
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 77ca4c6b087..531cb9790d3 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -505,14 +505,14 @@ int AArch64TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, if (Factor <= TLI->getMaxSupportedInterleaveFactor()) { unsigned NumElts = VecTy->getVectorNumElements(); - Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor); - unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy); + auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor); // ldN/stN only support legal vector types of size 64 or 128 in bits. // Accesses having vector types that are a multiple of 128 bits can be // matched to more than one ldN/stN instruction. - if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize % 128 == 0)) - return Factor * ((SubVecSize + 127) / 128); + if (NumElts % Factor == 0 && + TLI->isLegalInterleavedAccessType(SubVecTy, DL)) + return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL); } return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, |