summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/AArch64/AArch64Subtarget.h
Commit message (Expand)AuthorAgeFilesLines
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-1/+2
* AArch64: add a pass to compress jump-table entries when possible.Tim Northover2018-10-241-0/+2
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-021-7/+7
* [AArch64][v8.5A] Add MTE as an optional AArch64 extensionOliver Stannard2018-10-021-0/+2
* [AArch64] Split zero cycle feature more granularlyEvandro Menezes2018-09-281-1/+5
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-271-0/+4
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+2
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-221-0/+7
* AArch64: Add FuseCryptoEOR fusion rulesMatthias Braun2018-09-191-0/+2
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-071-7/+4
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-171-0/+2
* [ARM][AArch64] Armv8.4-A EnablementSjoerd Meijer2018-06-291-0/+14
* [AArch64] Support reserving x20 registerPetr Hosek2018-06-121-0/+4
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* [PATCH] [AArch64] Add new target feature to fuse conditional selectEvandro Menezes2018-02-231-1/+3
* [AArch64] Add new target feature to fuse address generation with load or storeEvandro Menezes2018-01-301-0/+2
* [AArch64] Add new target feature to handle cheap as move for ExynosEvandro Menezes2018-01-301-0/+2
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-301-0/+1
* [AArch64] Enable aggressive FMA on T99 and provide AArch64 options for others.Joel Jones2018-01-251-0/+2
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-191-0/+2
* Revert "AArch64: Fix emergency spillslot being out of reach for large callfra...Matthias Braun2018-01-101-2/+0
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-101-0/+2
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-7/+0
* AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover2017-12-181-0/+5
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier2017-09-251-0/+1
* [AArch64][Falkor] Avoid generating STRQro* instructionsGeoff Berry2017-08-281-0/+2
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-211-0/+2
* Reapply "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-151-10/+10
* [AArch64] Assembler support for v8.3 RCpcSam Parker2017-08-101-0/+2
* [ARM][AArch64] ARMv8.3-A enablementSam Parker2017-08-101-0/+2
* [AArch64] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer2017-08-091-0/+2
* Revert "[GlobalISel] Remove the GISelAccessor API."Quentin Colombet2017-08-081-10/+10
* [GlobalISel] Remove the GISelAccessor API.Quentin Colombet2017-08-041-10/+10
* [AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as wellMartin Storsjo2017-07-171-0/+11
* [AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson2017-07-131-0/+2
* [AArch64] Add AArch64Subtarget::isFusion function.Florian Hahn2017-07-121-0/+7
* [globalisel][tablegen] Demote OptForSize/OptForMinSize/ForCodeSize to per-fun...Daniel Sanders2017-05-191-5/+1
* [SLP] Enable 64-bit wide vectorization on AArch64Adam Nemet2017-05-151-0/+7
* [AArch64] Consider widening instructions in cost calculationsMatthew Simpson2017-05-091-0/+3
* [globalisel][tablegen] Compute available feature bits correctly.Daniel Sanders2017-04-291-1/+5
* AArch64: support nonlazybindTim Northover2017-04-171-0/+3
* [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsiaPetr Hosek2017-04-041-0/+12
OpenPOWER on IntegriCloud