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path: root/llvm/lib/Target/AArch64/AArch64Subtarget.h
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* [AARch64] Add Marvell ThunderX3T110 supportWei Zhao2020-06-171-1/+2
* AArch64: add missing Apple CPU names and use them by default.Tim Northover2020-01-081-1/+5
* [RAGreedy] Enable -consider-local-interval-cost for AArch64Sanne Wouda2019-11-081-0/+2
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-1/+0
* [AArch64] Adding support for PMMIR_EL1 registerVictor Campos2019-10-181-0/+2
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-10-091-4/+4
* Revert r372893 "[CodeGen] Replace -max-jump-table-size with -max-jump-table-t...Hans Wennborg2019-09-271-2/+2
* [CodeGen] Replace -max-jump-table-size with -max-jump-table-targetsEvandro Menezes2019-09-251-2/+2
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-0/+8
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-4/+6
* [GlobalISel] Make the InstructionSelector instance non-const, allowing state ...Amara Emerson2019-08-131-1/+1
* AArch64: Add a tagged-globals backend feature.Peter Collingbourne2019-07-311-0/+1
* SelectionDAG, MI, AArch64: Widen target flags fields/arguments from unsigned ...Peter Collingbourne2019-07-311-4/+4
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-311-0/+2
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-261-0/+4
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-0/+3
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-2/+0
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-0/+2
* Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"David Greene2019-07-101-4/+4
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-07-101-4/+4
* [AArch64] Subtarget crypto extension defaultsSjoerd Meijer2019-05-221-6/+6
* [AArch64][SVE2] Add SVE2 target features to backend and TargetParserCullen Rhodes2019-05-131-0/+13
* [AArch64] Allow -mattr=tpidr-el[1|2|3]Oliver Stannard2019-03-211-0/+7
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] Add new target feature to fuse arithmetic and logic operationsEvandro Menezes2019-01-141-3/+6
* [AArch64] Move feature predctrl to predresDiogo N. Sampaio2019-01-091-2/+2
* [AArch64] Add command-line option for SBDiogo N. Sampaio2018-12-281-2/+2
* [NFC][AArch64] Split out backend featuresDiogo N. Sampaio2018-12-061-0/+51
* AArch64: support funclets in fastcall and swift_callSaleem Abdulrasool2018-12-051-0/+2
* Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend featuresSimon Pilgrim2018-12-041-51/+0
* [AArch64] Add command-line option for SSBSPablo Barrio2018-12-031-0/+2
* [NFC][AArch64] Split out backend featuresDiogo N. Sampaio2018-12-031-0/+51
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-1/+2
* AArch64: add a pass to compress jump-table entries when possible.Tim Northover2018-10-241-0/+2
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-021-7/+7
* [AArch64][v8.5A] Add MTE as an optional AArch64 extensionOliver Stannard2018-10-021-0/+2
* [AArch64] Split zero cycle feature more granularlyEvandro Menezes2018-09-281-1/+5
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-271-0/+2
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-271-0/+4
* [ARM/AArch64][v8.5A] Add Armv8.5-A targetOliver Stannard2018-09-261-0/+2
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-221-0/+7
* AArch64: Add FuseCryptoEOR fusion rulesMatthias Braun2018-09-191-0/+2
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-071-7/+4
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