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* AMDGPU: Fix various issues around the VirtReg2Value mappingNicolai Haehnle2018-11-301-29/+36
* [MachineOutliner] Outline both register save calls + no LR save calls togetherJessica Paquette2018-11-301-32/+26
* AArch64: Don't emit CFI for SCS register in nounwind functions.Peter Collingbourne2018-11-301-14/+16
* [X86] Change vXi8 MULHU lowering to unpack high and low half of lanes instead...Craig Topper2018-11-301-54/+47
* [X86] Prefer lowerVectorShuffleAsBitMask over using a avx512 masked operation...Craig Topper2018-11-301-5/+5
* [AMDGPU] Disable SReg Global LD/ST, perf regressionRon Lieberman2018-11-301-0/+7
* [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin2018-11-3012-50/+711
* [RISCV] Add additional CSR instruction aliases (imm. operands)Alex Bradbury2018-11-301-0/+10
* [RISCV] Add UNIMP instruction (32- and 16-bit forms)Alex Bradbury2018-11-302-0/+17
* [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement fo...Alex Bradbury2018-11-302-0/+5
* [RISCV] Introduce codegen patterns for instructions introduced in RV64IAlex Bradbury2018-11-302-1/+99
* [X86] Emit PACKUS directly from the v16i8 LowerMULH code instead of using a s...Craig Topper2018-11-301-6/+1
* [X86] Change the pre-sse4.1 code in the v16i8 MULHU lowering to be what we ge...Craig Topper2018-11-301-13/+18
* [ARM] Don't expand sdiv when optimising for minsizeSjoerd Meijer2018-11-302-0/+47
* [SystemZ::TTI] i8/i16 operands extension costs revisitedJonas Paulsson2018-11-301-20/+16
* [X86] Fix a couple types in SimplifyDemandedVectorEltsForTargetNode. NFCICraig Topper2018-11-301-3/+3
* Fix build warnings introduced in rL347938Mircea Trofin2018-11-301-1/+3
* Revert "Revert r347596 "Support for inserting profile-directed cache prefetch...Mircea Trofin2018-11-306-1/+397
* [WebAssembly] Expand unavailable integer operations for vectorsThomas Lively2018-11-291-6/+14
* Produce an error on non-encodable offsets for darwin ARM scattered relocations.Jonas Devlieghere2018-11-291-0/+20
* [RISCV] Implement codegen for cmpxchg on RV32IAAlex Bradbury2018-11-294-1/+178
* [X86] Change the pre-type legalization DAG combine added in r347898 into a cu...Craig Topper2018-11-291-49/+33
* Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard2018-11-2911-545/+54
* [MachineScheduler] Order FI-based memops based on stack directionFrancis Visoiu Mistrih2018-11-291-5/+8
* [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from Leg...Craig Topper2018-11-293-85/+38
* [X86] Add a DAG combine pre type legalization to widen division by constant s...Craig Topper2018-11-291-0/+39
* [AMDGPU] Add and update scalar instructionsGraham Sellers2018-11-294-34/+214
* Fix: Add support for TFE/LWE in image intrinsicDavid Stuttard2018-11-291-2/+1
* Add support for TFE/LWE in image intrinsicsDavid Stuttard2018-11-2911-54/+546
* Revert r347596 "Support for inserting profile-directed cache prefetches"Hans Wennborg2018-11-296-395/+1
* [GlobalISel] Make EnableGlobalISel always set when GISel is enabledPetr Pavlu2018-11-291-1/+3
* [llvm-mca][MC] Add the ability to declare which processor resources model loa...Andrea Di Biagio2018-11-291-0/+4
* AMDGPU/InsertWaitcnts: Remove the dependence on MachineLoopInfoNicolai Haehnle2018-11-291-469/+256
* AMDGPU/InsertWaitcnt: Consistently use uint32_t for scores / time pointsNicolai Haehnle2018-11-291-55/+49
* AMDGPU/InsertWaitcnt: Remove unused WaitAtBeginningNicolai Haehnle2018-11-291-27/+2
* AMDGPU/InsertWaitcnts: Simplify pending events trackingNicolai Haehnle2018-11-291-191/+59
* AMDGPU/InsertWaitcnts: Use foreach loops for inst and wait event typesNicolai Haehnle2018-11-291-26/+39
* AMDGPU/InsertWaitcnts: Untangle some semi-global stateNicolai Haehnle2018-11-293-242/+234
* [X86] Correct comment. NFCCraig Topper2018-11-291-1/+1
* [PowerPC] Fix a conversion is not considered when the ISD::BR_CC node making ...Li Jia He2018-11-291-0/+9
* [x86] try select simplification for target-specific nodesSanjay Patel2018-11-281-1/+6
* [X86] Make X86TTIImpl::getCastInstrCost properly handle the case where AVX512...Craig Topper2018-11-281-23/+25
* [X86] Add some cost model entries for sext/zext for avx512bwCraig Topper2018-11-281-0/+27
* [X86] Add a combine for back to back VSRAI instructionsCraig Topper2018-11-281-0/+11
* [RISCV] Support .option push and .option popAlex Bradbury2018-11-285-1/+62
* [MachineScheduler] Add support for clustering mem ops with FI base operandsFrancis Visoiu Mistrih2018-11-281-23/+77
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-2813-136/+173
* [DebugInfo] Rename EmitDebugThreadLocal back to EmitDebugValue. NFCSimon Atanasyan2018-11-282-3/+2
* [SystemZ::TTI] Improve cost for compare of i64 with extended i32 loadJonas Paulsson2018-11-281-7/+9
* [SystemZ::TTI] Improve costs for i16 add, sub and mul against memory.Jonas Paulsson2018-11-281-4/+6
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