bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.	Quentin Colombet	2017-11-02	1	-1/+14
*	[AArch64][RegisterBankInfo] Add FPR16 support in value mapping.	Quentin Colombet	2017-11-02	1	-6/+6
*	[RegisterBankInfo] Uniquely allocate instruction mapping.	Quentin Colombet	2017-05-05	1	-3/+4
*	GlobalISel: fall back gracefully when we can't map an operand's size.	Tim Northover	2017-02-06	1	-4/+5
*	Re-commit: [globalisel] Tablegen-erate current Register Bank Information	Daniel Sanders	2017-01-19	1	-18/+11
*	Re-revert: [globalisel] Tablegen-erate current Register Bank Information	Daniel Sanders	2017-01-18	1	-11/+18
*	Re-commit: [globalisel] Tablegen-erate current Register Bank Information	Daniel Sanders	2017-01-18	1	-18/+11
*	Revert r292132: [globalisel] Tablegen-erate current Register Bank Information...	Daniel Sanders	2017-01-16	1	-11/+18
*	[globalisel] Tablegen-erate current Register Bank Information	Daniel Sanders	2017-01-16	1	-18/+11
*	[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather t...	Daniel Sanders	2017-01-13	1	-13/+11
*	[aarch64][globalisel] Move getValueMapping/getCopyMapping to AArch64GenRegist...	Daniel Sanders	2017-01-13	1	-45/+22
*	[aarch64][globalisel] Refactor getRegBankBaseIdxOffset() to remove the power-...	Daniel Sanders	2017-01-13	1	-0/+23
*	[aarch64][globalisel] Move data into <Target>GenRegisterBankInfo. NFC.	Daniel Sanders	2017-01-13	1	-5/+66
*	[AArch64][GlobalISel] Remove redundant RBI comments. NFC.	Ahmed Bougacha	2016-12-15	1	-20/+1
*	[AArch64][RegisterBankInfo] Add getSameKindofOperandsMapping.	Quentin Colombet	2016-10-03	1	-0/+10
*	[RegisterBankInfo] Move to statically allocated RegisterBank.	Quentin Colombet	2016-09-22	1	-0/+4
*	[AArch64] Mark various *Info classes as 'final'. NFC.	Ahmed Bougacha	2016-07-27	1	-1/+1
*	GlobalISel: implement low-level type with just size & vector lanes.	Tim Northover	2016-07-20	1	-0/+2
*	[AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR.	Quentin Colombet	2016-06-08	1	-0/+8
*	[RegisterBankInfo] Add a size argument for the cost of copy.	Quentin Colombet	2016-06-08	1	-3/+7
*	[AArch64] Teach RegisterBankInfo about the CC register bank.	Quentin Colombet	2016-04-07	1	-0/+1
*	[AArch64] Teach RegisterBankInfo about the mapping of register classes	Quentin Colombet	2016-04-07	1	-0/+15
*	[AArch64] Initial implementation of the targeting of the register bank inform...	Quentin Colombet	2016-04-05	1	-0/+41