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path: root/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
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* GlobalISel: Add type argument to getRegBankFromRegClassMatt Arsenault2020-01-031-2/+3
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-051-1/+1
* [AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.Amara Emerson2019-08-131-1/+1
* [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-5/+5
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-2/+2
* [AArch64][GlobalISel] Add support for s128 loads, stores, extracts, truncs.Amara Emerson2019-07-231-0/+15
* [GlobalISel][AArch64] Save a copy on G_SELECT by fixing condition to GPRJessica Paquette2019-07-231-5/+3
* [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immedi...Amara Emerson2019-07-031-4/+11
* [GlobalISel][AArch64] Make FP constraint checks consider possible use/def banksJessica Paquette2019-05-241-7/+35
* [GlobalISel][AArch64] NFC: Factor out HasFPConstraints into a proper functionJessica Paquette2019-05-241-41/+28
* [GlobalISel][AArch64] Improve register bank mappings for G_SELECTJessica Paquette2019-05-241-6/+49
* [AArch64][GlobalISel] Use fcsel instead of csel for G_SELECT on FPRsJessica Paquette2019-05-031-18/+33
* [GlobalISel][AArch64] Legalize G_FNEARBYINTJessica Paquette2019-04-251-0/+1
* [AArch64][GlobalISel] Mark G_INTRINSIC_ROUND as a pre-isel floating point opcodeJessica Paquette2019-04-231-0/+1
* [AArch64][GlobalISel] Teach regbankselect about G_INTRINSIC_TRUNCJessica Paquette2019-04-231-0/+1
* [AArch64][GlobalISel] Add G_FMA to isPreISelGenericFloatingPointOpcodeJessica Paquette2019-04-231-0/+1
* [GlobalISel][AArch64] Legalize + select G_FRINTJessica Paquette2019-04-191-0/+1
* [AArch64][GlobalISel] Regbankselect: Fix G_BUILD_VECTOR trying to use s16 gpr...Amara Emerson2019-03-151-2/+5
* [GlobalISel][AArch64] Add partial selection support for G_INSERT_VECTOR_ELTJessica Paquette2019-03-141-0/+12
* Recommit "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"Jessica Paquette2019-03-111-0/+8
* Revert "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"Jessica Paquette2019-03-051-8/+0
* [GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELTJessica Paquette2019-03-041-0/+8
* [AArch64] Support reserving arbitrary general purpose registersPetr Hosek2019-02-131-0/+2
* [GlobalISel][AArch64] Select G_FFLOORJessica Paquette2019-02-111-0/+1
* [GlobalISel][AArch64] Select G_FEXPJessica Paquette2019-01-301-0/+1
* [GlobalISel][AArch64] Select G_FABSJessica Paquette2019-01-301-0/+1
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log2Jessica Paquette2019-01-301-0/+1
* [GlobalISel][AArch64] Add instruction selection support for @llvm.sqrtJessica Paquette2019-01-301-0/+1
* [AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank.Amara Emerson2019-01-291-1/+5
* [GlobalISel][AArch64] Add legalization for G_FLOGJessica Paquette2019-01-281-0/+1
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log10Jessica Paquette2019-01-281-0/+1
* [GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSINJessica Paquette2019-01-281-0/+2
* [AArch64][GlobalISel] Teach RBS about G_FNEG default mapping.Amara Emerson2019-01-281-0/+1
* [AArch64][GlobalISel] Add some vector support for fp <-> int conversions.Amara Emerson2019-01-281-0/+4
* [GlobalISel][AArch64] Add isel support for FP16 vector @llvm.ceilJessica Paquette2019-01-241-0/+56
* hwasan: Move memory access checks into small outlined functions on aarch64.Peter Collingbourne2019-01-231-0/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [GlobalISel][AArch64] Add G_FCEIL to isPreISelGenericFloatingPointOpcodeJessica Paquette2018-12-201-0/+1
* [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPRQuentin Colombet2017-11-181-2/+11
* [AArch64] Map G_STORE on FPR when the source comes from a FPR copyQuentin Colombet2017-11-181-1/+9
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-3/+3
* [AArch64][RegisterBankInfo] Add mapping for G_FPEXT.Quentin Colombet2017-11-021-0/+32
* [AArch64][RegisterBankInfo] Add FPR16 support in value mapping.Quentin Colombet2017-11-021-3/+5
* [aarch64][globalisel] Register banks and classes should have distinct names.Daniel Sanders2017-10-181-4/+3
* Re-apply [AArch64][RegisterBankInfo] Use the statically computed mappings for...Quentin Colombet2017-10-161-4/+35
* [AArch64][RegisterBankInfo] Add mapping support for G_BITCAST of s128Quentin Colombet2017-10-161-2/+2
* Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for ...Bruno Cardoso Lopes2017-10-141-32/+4
* [AArch64][RegisterBankInfo] Use the statically computed mappings for COPYQuentin Colombet2017-10-141-4/+32
* [GISEl]: Translate phi into G_PHIAditya Nandakumar2017-08-231-1/+2
* [GlobalISel] Make GlobalISel a non-optional library.Quentin Colombet2017-08-031-4/+0
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