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* Move the complex address expression out of DIVariable and into an extraAdrian Prantl2014-10-011-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | argument of the llvm.dbg.declare/llvm.dbg.value intrinsics. Previously, DIVariable was a variable-length field that has an optional reference to a Metadata array consisting of a variable number of complex address expressions. In the case of OpPiece expressions this is wasting a lot of storage in IR, because when an aggregate type is, e.g., SROA'd into all of its n individual members, the IR will contain n copies of the DIVariable, all alike, only differing in the complex address reference at the end. By making the complex address into an extra argument of the dbg.value/dbg.declare intrinsics, all of the pieces can reference the same variable and the complex address expressions can be uniqued across the CU, too. Down the road, this will allow us to move other flags, such as "indirection" out of the DIVariable, too. The new intrinsics look like this: declare void @llvm.dbg.declare(metadata %storage, metadata %var, metadata %expr) declare void @llvm.dbg.value(metadata %storage, i64 %offset, metadata %var, metadata %expr) This patch adds a new LLVM-local tag to DIExpressions, so we can detect and pretty-print DIExpression metadata nodes. What this patch doesn't do: This patch does not touch the "Indirect" field in DIVariable; but moving that into the expression would be a natural next step. http://reviews.llvm.org/D4919 rdar://problem/17994491 Thanks to dblaikie and dexonsmith for reviewing this patch! llvm-svn: 218778
* [AArch64] Improve AA to remove unneeded edges in the AA MI scheduling graph.Chad Rosier2014-09-081-0/+132
| | | | | | | Patch by Sanjin Sijaric <ssijaric@codeaurora.org>! Phabricator Review: http://reviews.llvm.org/D5103 llvm-svn: 217371
* Remove unnecessary getTarget call now that the subtarget is cachedEric Christopher2014-09-031-1/+1
| | | | | | on the machine function. llvm-svn: 217070
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Reapply r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-09-031-79/+128
| | | | | | | | | | | | | | | | for MADD, SUB, and OR."" This reapplies r216805 with a fix to a copy-past error, which resulted in an incorrect register class. Original commit message: Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 217019
* Revert r216805 "[MachineCombiner][AArch64] Use the correct register class ↵Juergen Ributzka2014-08-301-119/+73
| | | | | | | | for MADD, SUB, and OR." I think this broke the build bot. Reverting it for now until I have time to take a closer look. llvm-svn: 216813
* [MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR.Juergen Ributzka2014-08-291-73/+119
| | | | | | | | | | Select the correct register class for the various instructions that are generated when combining instructions and constrain the registers to the appropriate register class. This fixes rdar://problem/18183707. llvm-svn: 216805
* [MachineCombiner] Removal of dangling DBG_VALUES after combining [20598]Gerolf Hoflehner2014-08-131-2/+1
| | | | | | | | This is a cleaner solution to the problem described in r215431. When instructions are combined a dangling DBG_VALUE is removed. This resolves bug 20598. llvm-svn: 215587
* [MachineCombiner] Fix for ICE bug 20598Gerolf Hoflehner2014-08-121-1/+2
| | | | | | | | | | | | | | | | | | The combiner ignored DBG nodes when checking the uses of a virtual register. It combined a sequence like %vreg1 = madd %vreg2, %vreg3,... DBG_VALUE (%vreg1 ...) %vreg4 = add %vreg1,... to %vreg4 = madd %vreg2, %vreg3 leaving behind a dangling DBG_VALUE with a definition. This triggered an assertion in the MachineTraceMetrics.cpp module. llvm-svn: 215431
* Resolving some type truncation warnings in MSVC (enum to bool in this case). ↵Aaron Ballman2014-08-091-3/+3
| | | | | | No functional changes intended. llvm-svn: 215293
* [AArch64] Fix a type conversion bug for anlyzing compare.Jiangning Liu2014-08-081-4/+13
| | | | | | | | The bug can cause spec2006/483.xalancbmk failure. Patched by David Xu. llvm-svn: 215206
* AArch64InstrInfo.cpp: Fix \param(s). [-Wdocumentation]NAKAMURA Takumi2014-08-081-2/+2
| | | | llvm-svn: 215180
* MachineCombiner Pass for selecting faster instruction sequence on AArch64Gerolf Hoflehner2014-08-071-10/+466
| | | | | | | | | | Re-commit of r214832,r21469 with a work-around that avoids the previous problem with gcc build compilers The work-around is to use SmallVector instead of ArrayRef of basic blocks in preservesResourceLen()/MachineCombiner.cpp llvm-svn: 215151
* Revert "r214832 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-051-466/+10
| | | | | | | It broke compiling of most Benchmark and internal test, as clang got clashed by segmentation fault or assertion. llvm-svn: 214845
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-051-10/+466
| | | | | | | | | | | sequence on AArch64 Re-commit of r214669 without changes to test cases LLVM::CodeGen/AArch64/arm64-neon-mul-div.ll and LLVM:: CodeGen/AArch64/dp-3source.ll This resolves the reported compfails of the original commit. llvm-svn: 214832
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+2
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Revert "r214669 - MachineCombiner Pass for selecting faster instruction"Kevin Qin2014-08-041-466/+10
| | | | | | This commit broke "make check" for several hours, so get it reverted. llvm-svn: 214697
* MachineCombiner Pass for selecting faster instructionGerolf Hoflehner2014-08-031-10/+466
| | | | | | | | | | | | | | | | | | | | | | sequence - AArch64 target support This patch turns off madd/msub generation in the DAGCombiner and generates them in the MachineCombiner instead. It replaces the original code sequence with the combined sequence when it is beneficial to do so. When there is no machine model support it always generates the madd/msub instruction. This is true also when the objective is to optimize for code size: when the combined sequence is shorter is always chosen and does not get evaluated. When there is a machine model the combined instruction sequence is evaluated for critical path and resource length using machine trace metrics and the original code sequence is replaced when it is determined to be faster. rdar://16319955 llvm-svn: 214669
* Add missing breaks to AArch64InstrInfo::isGPRCopyRenato Golin2014-08-011-0/+3
| | | | llvm-svn: 214528
* Implement AArch64 TTI interface isAsCheapAsAMove.Jiangning Liu2014-07-291-0/+45
| | | | llvm-svn: 214159
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-251-0/+50
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-181-1/+1
| | | | llvm-svn: 211141
* AArch64: estimate inline asm length during branch relaxationTim Northover2014-06-171-1/+7
| | | | | | | | | | | | | To make sure branches are in range, we need to do a better job of estimating the length of an inline assembly block than "it's probably 1 instruction, who'd write asm with more than that?". Fortunately there's already a (highly suspect, see how many ways you can think of to break it!) callback for this purpose, which is used by the other targets. rdar://problem/17277590 llvm-svn: 211095
* Remove a method that was just replacing direct access to a member.Eric Christopher2014-06-101-18/+18
| | | | llvm-svn: 210598
* Remove the uses of AArch64TargetMachine and AArch64Subtarget fromEric Christopher2014-06-101-1/+1
| | | | | | AArch64FrameLowering. llvm-svn: 210548
* AArch64: implement copies to/from NZCV as a last ditch effort.Tim Northover2014-05-271-1/+19
| | | | | | | | | | A test in test/Generic creates a DAG where the NZCV output of an ADCS is used by multiple nodes. This makes LLVM want to save a copy of NZCV for later, which it couldn't do before. This should be the last fix required for the aarch64 buildbot. llvm-svn: 209651
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+2065
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-241-979/+0
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-3/+3
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition llvm-svn: 207510
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-2/+2
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* Simplify. No functionality change.Rafael Espindola2014-03-071-4/+1
| | | | llvm-svn: 203202
* [AArch64]Add support for spilling FPR8/FPR16.Hao Liu2014-02-131-0/+8
| | | | llvm-svn: 201287
* [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two ↵Hao Liu2014-02-101-0/+10
| | | | | | FPR32 registers in copyPhysReg. llvm-svn: 201061
* Fix known typosAlp Toker2014-01-241-1/+2
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-241-2/+2
| | | | llvm-svn: 199978
* [AArch64]Fix the problem can't select f16_to_f32 and f32_to_f16.Hao Liu2014-01-171-0/+10
| | | | | | | Also add copy support for FPR16. Also add a missing test case file belongs to commit r197361. llvm-svn: 199463
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+0
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. ↵Hao Liu2014-01-071-8/+31
| | | | | | There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed. llvm-svn: 198684
* [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q ↵Hao Liu2014-01-071-1/+51
| | | | | | tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed. llvm-svn: 198682
* [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.Hao Liu2013-12-301-8/+50
| | | | llvm-svn: 198193
* [AArch64]Implement 128 bit register copy with NEON.Kevin Qin2013-11-261-17/+19
| | | | llvm-svn: 195713
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+1
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+1
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-1/+1
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-171-14/+40
| | | | llvm-svn: 190839
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-161-11/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-071-1/+1
| | | | | | These objects are internal to the TargetMachine object and may change. llvm-svn: 183485
* Switch to LLVM support function abs64 to keep VS2008 happy.Tim Northover2013-03-271-3/+3
| | | | llvm-svn: 178141
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