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path: root/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
Commit message (Expand)AuthorAgeFilesLines
* DAG: Use TargetConstant for FENCE operandsMatt Arsenault2020-01-021-3/+3
* [GlobalISel][AArch64] Select llvm.aarch64.stxr* intrinsics.Jessica Paquette2019-08-291-4/+12
* [GlobalISel][AArch64] Use a GISelPredicateCode to select llvm.aarch64.stlxr.*Jessica Paquette2019-08-291-5/+12
* [AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsicsJessica Paquette2019-08-291-4/+12
* [AArch64][GlobalISel] Select @llvm.aarch64.ldaxr.* intrinsicsJessica Paquette2019-08-291-4/+12
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] Improve v8.1-A code-gen for atomic load-andOliver Stannard2018-02-121-1/+6
* [globalisel][tablegen] Add support for relative AtomicOrderingsDaniel Sanders2017-11-301-18/+16
* [AArch64] LSE Atomics reorg - part 1Joel Jones2017-08-051-54/+14
* [AArch64] Standardize suffixes for LSE Atomics mnemonics (NFCI)Joel Jones2017-07-281-54/+54
* [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomicsMatthew Simpson2017-07-131-0/+10
* [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.Christof Douma2017-06-211-0/+46
* AArch64: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-201-0/+3
* AArch64: properly calculate cmpxchg status in FastISel.Tim Northover2016-08-021-7/+7
* AArch64: expand cmpxchg after regalloc at -O0.Tim Northover2016-04-141-0/+40
* NFC: make AtomicOrdering an enum classJF Bastien2016-04-061-5/+6
* Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backendsRobin Morisset2014-08-181-5/+4
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+364
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