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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in TargetLowering...Craig Topper2016-04-281-7/+0
* [AArch64] Expand CTTZ for all vector types.Craig Topper2016-04-281-0/+9
* [CodeGen] Add getBuildVector and getSplatBuildVector helpers. NFCI.Ahmed Bougacha2016-04-261-14/+12
* [AArch64] Expand v1i64 and v2i64 ctlz.Craig Topper2016-04-261-0/+3
* [AArch64] [ARM] Make a target-independent llvm.thread.pointer intrinsic.Marcin Koscielnicki2016-04-191-3/+3
* [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARDTim Shen2016-04-191-1/+3
* Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.Craig Topper2016-04-151-52/+51
* AArch64: expand cmpxchg after regalloc at -O0.Tim Northover2016-04-141-1/+36
* TargetLowering: Factor out common code for tail call eligibility checking; NFCMatthias Braun2016-04-141-21/+3
* AArch64: Use a callee save registers for swiftself parametersMatthias Braun2016-04-131-6/+32
* AArch64: Drive-by cleanupMatthias Braun2016-04-121-3/+2
* [SSP] Remove llvm.stackprotectorcheck.Tim Shen2016-04-081-2/+2
* NFC: make AtomicOrdering an enum classJF Bastien2016-04-061-2/+2
* Faster stack-protector for Android/AArch64.Evgeniy Stepanov2016-04-051-0/+16
* ARM, AArch64, X86: Check preserved registers for tail calls.Matthias Braun2016-04-041-7/+7
* AArch64ISelLowering: Remove unused variables/arguments; NFCMatthias Braun2016-04-011-4/+1
* CodeGen: Factor out code for tail call result compatibility check; NFCMatthias Braun2016-03-301-34/+9
* [AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optim...Haicheng Wu2016-03-281-0/+17
* [CXX_FAST_TLS] Disable tail call when calling conventions are mismatched.Manman Ren2016-03-181-0/+7
* [CXX_FAST_TLS] fix issues with O0 on ARM, AArch64 and X86.Manman Ren2016-03-181-0/+1
* [DAG] use !isUndef() ; NFCISanjay Patel2016-03-141-1/+1
* [DAG] use isUndef() ; NFCISanjay Patel2016-03-141-7/+6
* [AArch64] Don't blindly lower f16/f128 FCCMPs.Ahmed Bougacha2016-03-111-3/+16
* AArch64: only try to use scaled fcvt ops on legal vector types.Tim Northover2016-03-101-1/+2
* Add support for a preserve_most calling convention to the AArch64 backend.Roman Levenstein2016-03-101-1/+3
* [AArch64] fold 'isPositive' vector integer operations (PR26819)Sanjay Patel2016-03-031-1/+30
* Revert "[AArch64] Fix isLegalAddImmediate() to return true for valid nega...Geoff Berry2016-03-011-2/+2
* Simplify some boolean conditional return statements in AArch64.Eric Christopher2016-02-291-24/+11
* [AArch64] Fix isLegalAddImmediate() to return true for valid negative values.Geoff Berry2016-02-291-2/+2
* [GlobalISel] Re-apply r260922-260923 with MSVC-friendly code.Quentin Colombet2016-02-161-78/+0
* Reverting r260922-260923; they cause link failures with MSVC.Aaron Ballman2016-02-161-0/+78
* [GlobalISel] Get rid of the ifdefs in TargetLowering.Quentin Colombet2016-02-161-78/+0
* [AArch64] Add support for Qualcomm Kryo CPU.Chad Rosier2016-02-121-1/+1
* [AArch64] Implements the lowering of formal arguments for GlobalISel.Quentin Colombet2016-02-111-0/+49
* [AArch64] Trivial implementation of lower return for the IRTranslator.Quentin Colombet2016-02-111-0/+29
* [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI.Ahmed Bougacha2016-02-091-12/+6
* AArch64: Implement missed conditional compare sequences.Balaram Makam2016-02-011-2/+45
* Silence a -Wparentheses warning; NFC.Junmo Park2016-01-251-2/+2
* Silence a -Wparentheses warning; NFC.Aaron Ballman2016-01-231-1/+1
* Inline variable into assertMatthias Braun2016-01-231-3/+1
* AArch64ISelLowering.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2016-01-231-0/+1
* AArch64ISel: Fix ccmp code selection matching deep expressions.Matthias Braun2016-01-231-48/+79
* AArch64ISelLowering: Reduce maximum recursion depth of isConjunctionDisjuncti...Matthias Braun2016-01-231-2/+2
* Fix wrong indentationMatthias Braun2016-01-231-4/+4
* [AArch64] Simplify emitConditionalCompare calls. NFC.Ahmed Bougacha2016-01-221-13/+9
* [AArch64] Lower 2-CC FCCMPs (one/ueq) using AND'ed CCs.Ahmed Bougacha2016-01-221-8/+36
* [AArch64] Assert that CCMP isel didn't fail inconsistently.Ahmed Bougacha2016-01-221-0/+2
* Do not lower VSETCC if operand is an f16 vectorPirama Arumuga Nainar2016-01-221-0/+3
* CXX_FAST_TLS calling convention: fix issue on AArch64.Manman Ren2016-01-151-4/+5
* Update to use new name alignTo().Rui Ueyama2016-01-141-5/+4
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