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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-03-11 22:02:58 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-03-11 22:02:58 +0000 |
| commit | 171f7b99865809b8ad738281ba21dec5d3839ede (patch) | |
| tree | 06d227aa108629af8bf58dedfd7bea7714f1e597 /llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | |
| parent | 8918372dd3acb81dbc092503d75c261b892df6a8 (diff) | |
| download | bcm5719-llvm-171f7b99865809b8ad738281ba21dec5d3839ede.tar.gz bcm5719-llvm-171f7b99865809b8ad738281ba21dec5d3839ede.zip | |
[AArch64] Don't blindly lower f16/f128 FCCMPs.
Instead, extend f16 (like we do when lowering a standalone SETCC),
and let f128 be legalized to the RT calls.
Fixes PR26803.
llvm-svn: 263301
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ecb8eb19c18..cb78d6ddb0f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1216,8 +1216,14 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) { EVT VT = LHS.getValueType(); - if (VT.isFloatingPoint()) + if (VT.isFloatingPoint()) { + assert(VT != MVT::f128); + if (VT == MVT::f16) { + LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); + RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); + } return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); + } // The CMP instruction is just an alias for SUBS, and representing it as // SUBS means that it's possible to get CSE with subtract operations. @@ -1301,9 +1307,14 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS, AArch64CC::CondCode OutCC, SDLoc DL, SelectionDAG &DAG) { unsigned Opcode = 0; - if (LHS.getValueType().isFloatingPoint()) + if (LHS.getValueType().isFloatingPoint()) { + assert(LHS.getValueType() != MVT::f128); + if (LHS.getValueType() == MVT::f16) { + LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); + RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); + } Opcode = AArch64ISD::FCCMP; - else if (RHS.getOpcode() == ISD::SUB) { + } else if (RHS.getOpcode() == ISD::SUB) { SDValue SubOp0 = RHS.getOperand(0); if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { // See emitComparison() on why we can only do this for SETEQ and SETNE. @@ -1333,6 +1344,8 @@ static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanNegate, return false; unsigned Opcode = Val->getOpcode(); if (Opcode == ISD::SETCC) { + if (Val->getOperand(0).getValueType() == MVT::f128) + return false; CanNegate = true; return true; } |

