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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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* merge vector stores into wider vector stores and fix AArch64 misaligned acces...Sanjay Patel2015-09-251-3/+23
* [AArch64] Emit clrex in the expanded cmpxchg fail block.Ahmed Bougacha2015-09-221-0/+7
* Improve ISel using across lane min/max reductionJun Bum Lim2015-09-141-53/+190
* [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.Ahmed Bougacha2015-09-111-4/+6
* [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.Ahmed Bougacha2015-09-111-3/+2
* Remove white space (test commit)Jun Bum Lim2015-09-081-1/+1
* [AArch64] Improve ISel using across lane addition reduction.Chad Rosier2015-09-031-0/+99
* [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.Ahmed Bougacha2015-09-011-0/+5
* AArch64: Fix loads to lower NEON vector lanes using GPR registersMatthias Braun2015-08-311-1/+4
* [AArch64] Unify the integer min/max vector selection patterns with the intrin...Silviu Baranga2015-08-261-0/+12
* AArch64: Fix cmp;ccmp orderingMatthias Braun2015-08-201-3/+10
* AArch64: Do not create CCMP on multiple users.Matthias Braun2015-08-201-1/+1
* Remove hand-rolled matching for fmin and fmax.James Molloy2015-08-171-98/+2
* [AArch64] FMINNAN/FMAXNAN on f16 is not legal.James Molloy2015-08-141-2/+4
* [AArch64] Also custom-lowering mismatched vector/f16 FCOPYSIGN.Ahmed Bougacha2015-08-131-11/+5
* PseudoSourceValue: Replace global manager with a manager in a machine function.Alex Lorenz2015-08-111-18/+25
* [AArch64] Match fminnum/fmaxnum for vector fminnm/fmaxnm instead of an intrin...James Molloy2015-08-111-2/+11
* [AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with ISD::FMINNAN/MAXNANJames Molloy2015-08-111-6/+9
* Fix some comment typos.Benjamin Kramer2015-08-081-2/+2
* wrap OptSize and MinSize attributes for easier and consistent access (NFCI)Sanjay Patel2015-08-041-4/+2
* [AArch64] Add isel support for f16 indexed LD/ST.Ahmed Bougacha2015-08-041-0/+2
* [AArch64] Remove unnecessary "break". NFC.Ahmed Bougacha2015-08-041-1/+0
* [AArch64] Use SDValue bool operator. NFC.Ahmed Bougacha2015-08-041-6/+3
* [AArch64] Vector FCOPYSIGN supports Custom-lowering: mark it as such.Ahmed Bougacha2015-08-041-1/+4
* Convert some AArch64 code to foreach loops. NFC.Pete Cooper2015-08-031-12/+11
* [AArch64] Define subtarget feature strict-align.Akira Hatanaka2015-07-291-19/+12
* fix TLI's combineRepeatedFPDivisors interface to return the minimum user thre...Sanjay Patel2015-07-281-2/+2
* Implement target independent TLS compatible with glibc's emutls.c.Chih-Hung Hsieh2015-07-281-0/+4
* Implement __builtin_thread_pointerAdhemerval Zanella2015-07-281-0/+17
* When lowering vector shifts a check is performed to see if the value to shift byLuke Cheeseman2015-07-241-13/+6
* Fix comment typo (test commit). NFCGeoff Berry2015-07-201-1/+1
* [AArch64] Use [SU]ABSDIFF nodes instead of intrinsics for ABD/ABAJames Molloy2015-07-171-18/+29
* AArch64: Implement conditional compare sequence matching.Matthias Braun2015-07-161-40/+270
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-091-2/+2
* Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT userMehdi Amini2015-07-091-1/+2
* Remove getDataLayout() from TargetLoweringMehdi Amini2015-07-091-12/+14
* Make isLegalAddressingMode() taking DataLayout as an argumentMehdi Amini2015-07-091-6/+6
* Make TargetLowering::getShiftAmountTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+1
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-62/+70
* [TargetLowering] StringRefize asm constraint getters.Benjamin Kramer2015-07-051-7/+5
* Add op_values() to iterate over the SDValue operands of an SDNode.Pete Cooper2015-06-261-2/+1
* [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch...Hao Liu2015-06-261-0/+154
* Fix "the the" in comments.Eric Christopher2015-06-191-2/+2
* Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."Matthias Braun2015-06-171-178/+36
* Clean up redundant copies of Triple objects. NFCDaniel Sanders2015-06-161-1/+1
* [AArch64] Generalize extract-high DUP extension to MOVI/MVNI.Ahmed Bougacha2015-06-161-15/+24
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-011-36/+178
* Re-commit of r238201 with fix for building with shared libraries.Luke Cheeseman2015-06-011-1/+2
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-3/+5
* Revert "Re-commit changes in r237579 with fix for bug breaking windows builds."Diego Novillo2015-05-261-2/+1
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