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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-09-01 16:23:45 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2015-09-01 16:23:45 +0000 |
| commit | b0ff6437cb7c3ecd15cb987c7b684e35568d8fc1 (patch) | |
| tree | 3ca9508a596de2ac54bba5d92dbd4cf0552da7a8 /llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | |
| parent | abdb2d2aba6777dd786dfaed7e4df41a025bd672 (diff) | |
| download | bcm5719-llvm-b0ff6437cb7c3ecd15cb987c7b684e35568d8fc1.tar.gz bcm5719-llvm-b0ff6437cb7c3ecd15cb987c7b684e35568d8fc1.zip | |
[AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0.
This matches the ARM behavior. In both cases, the register is part
of the optional Performance Monitors extension, so, add the feature,
and enable it for the A-class processors we support.
Differential Revision: http://reviews.llvm.org/D12425
llvm-svn: 246555
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 4198071e3d6..20ed0016a79 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -399,6 +399,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::PREFETCH, MVT::Other, Custom); + // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0. + // This requires the Performance Monitors extension. + if (Subtarget->hasPerfMon()) + setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); + if (Subtarget->isTargetMachO()) { // For iOS, we don't want to the normal expansion of a libcall to // sincos. We want to issue a libcall to __sincos_stret to avoid memory |
